Language Reference 5
*ESE
*ESE?
This command programs the Standard Event Status Enable register bits. The programming determines which events of the Standard Event Status Event register (see *ESR?) are allowed to set the ESB (Event Summary Bit) of the Status Byte register. A "1" in the bit position enables the corresponding event.
All of the enabled events of the Standard Event Status Event Register are logically
Bit Position | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bit Value | 128 | − | 32 | 16 | 8 | 4 | − | 1 |
Bit Name | PON | − | CME | EXE | DDE | QUE | − | OPC |
PON = |
| DDE = |
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CME = Command error |
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| QUE = Query error |
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EXE = Execution error |
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| OPC = Operation complete |
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*ESR?
This query reads the Standard Event Status Event register. Reading the register clears it. The bit configuration is the same as the Standard Event Status Enable register (see *ESE).
*OPC
*OPC?
This command causes the instrument to set the OPC bit (bit 0) of the Standard Event Status register when the instrument has completed all pending operations. Pending operations are complete when:
All commands sent before *OPC have been executed. This includes overlapped commands. Most commands are sequential and are completed before the next command is executed. Commands that affect output voltage, current or state, relays, and trigger actions are executed in parallel (or overlapped) with subsequent commands sent to the power supply. The *OPC command provides notification that all overlapped commands have been completed.
All triggered actions are completed
*OPC does not prevent processing of subsequent commands, but bit 0 will not be set until all pending operations are completed.
*OPC? causes the instrument to place an ASCII "1" in the Output Queue when all pending operations are completed. Unlike *OPC, *OPC? prevents processing of all subsequent commands. It can be used at the end of a command line so that the program can monitor the bus for data until it receives the "1" from the Output Queue.
Series N5700 User’s Guide | 75 |