AMD 8 Advanced 266 FSB AMD Athlon System Bus AC Characteristics, Preliminary Information, Chapter

Preliminary Information

25175H —March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet

6.3Advanced 266 FSB AMD Athlon™ System Bus AC Characteristics

The AC characteristics for the AMD Athlon system bus of this processor are shown in Table 4. The parameters are grouped based on the source or destination of the signals involved.

Table 4.	AMD Athlon™ System Bus AC Characteristics
Group			Symbol	Parameter	Min	Max	Units	Notes
All Signals		TRISE		Output Rise Slew Rate	1	3	V/ns	1
		TFALL		Output Fall Slew Rate	1	3	V/ns	1
		TSKEW-SAMEEDGE		Output skew with respect to	–	385	ps	2
				the same clock edge
		TSKEW-DIFFEDGE		Output skew with respect to a	–	770	ps	2
				different clock edge
Forward
		T	SU	Input Data Setup Time	300		ps	3
Clocks
		THD		Input Data Hold Time	300		ps	3
		CIN		Capacitance on input Clocks	4	25	pF
		COUT		Capacitance on output Clocks	4	12	pF
		TVAL		RSTCLK to Output Valid	250	2000	ps	4, 5
Sync		TSU		Setup to RSTCLK	500		ps	4, 6
		THD		Hold from RSTCLK	1000		ps	4, 6
Notes:
1. Rise and fall time ranges are guidelines over which the I/O has been characterized.
2. TSKEW-SAMEEDGEis the maximum skew within a clock forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to the same clock edge.
TSKEW-DIFFEDGEis the maximum skew within a clock forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to different clock edges.
3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.
4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST.
5. TVAL is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.
6. TSU is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge of
RSTCLK.

Chapter 6 Advanced 266 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications 25