AMD 8 Preliminary Information, FLUSH# Pin, IGNNE# Pin, INIT# Pin, INTR Pin, JTAG Pins, Chapter

Preliminary Information

25175H —March 2003 AMD Athlon™ XP Processor Model 8 Data Sheet

See “Frequency Identification (FID[3:0])” on page 33 for the

DC characteristics for FID[3:0].

FSB_Sense[1:0] Pins FSB_Sense[1:0] pins are either open circuit (logic level of 1) or are pulled to ground (logic level of 0) on the processor package with a 1 kΩ resistor. In conjunction with a circuit on the motherboard, these pins may be used to automatically detect the front-side bus (FSB) setting of this processor. Proper detection of the FSB setting requires the implementation of a pull-up resistor on the motherboard. Refer to the AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363 and the technical note FSB_Sense Auto Detection Circuitry for Desktop Processors, order# TN26673 for more information.

Table 27 is the truth table to determine the FSB of desktop processors.

Table 27. Front-Side Bus Sense Truth Table

FSB_Sense[1]	FSB_Sense[0]	Bus Frequency
1	0	RESERVED
1	1	133 MHz
0	1	166 MHz
0	0	RESERVED

	The FSB_Sense[1:0] pins are 3.3-V tolerant.
FLUSH# Pin	FLUSH# must be tied to VCC_CORE with a pullup resistor. If a
	debug connector is implemented, FLUSH# is routed to the
	debug connector.
IGNNE# Pin	IGNNE# is an input from the system that tells the processor to
	ignore numeric errors.
INIT# Pin	INIT# is an input from the system that resets the integer
	registers without affecting the floating-point registers or the
	internal caches. Execution starts at 0_FFFF_FFF0h.
INTR Pin	INTR is an input from the system that causes the processor to
	start an interrupt acknowledge transaction that fetches the
	8-bit interrupt vector and starts execution at that location.
JTAG Pins	TCK, TMS, TDI, TRST#, and TDO are the JTAG interface.
	Connect these pins directly to the motherboard debug
	connector. Pull TDI, TCK, TMS, and TRST# up to VCC_CORE with
	pullup resistors.

Chapter 11 Pin Descriptions 77