AMD 8 SYSCLK and SYSCLK# DC Characteristics, Preliminary Information, Chapter, Electrical Data

Models: 8

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8.9SYSCLK and SYSCLK# DC Characteristics

Preliminary Information

25175H —March 2003

AMD Athlon™ XP Processor Model 8 Data Sheet

8.9SYSCLK and SYSCLK# DC Characteristics

Table 14 shows the DC characteristics of the SYSCLK and SYSCLK# differential clocks. The SYSCLK signal represents CLKIN and RSTCLK tied together while the SYSCLK# signal represents CLKIN# and RSTCLK# tied together. For information about SYSCLK and SYSCLK#, see “SYSCLK and SYSCLK#” on page 79 and Table 24, “Pin Name Abbreviations,” on page 58.

Table 14. SYSCLK and SYSCLK# DC Characteristics

Symbol

Description

Min

Max

Units

 

 

 

 

 

VThreshold-DC

Crossing before transition is detected (DC)

400

 

mV

VThreshold-AC

Crossing before transition is detected (AC)

450

 

mV

ILEAK_P

Leakage current through P-channel pullup to VCC_CORE

–1

 

mA

ILEAK_N

Leakage current through N-channel pulldown to VSS (Ground)

 

1

mA

VCROSS

Differential signal crossover

 

VCC_CORE / 2±100

mV

CPIN

Capacitance *

4

25 *

pF

Note:

* The following processor inputs have twice the listed capacitance because they connect to two input pads—SYSCLK and SYSCLK#. SYSCLK connects to CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#.

Figure 11 shows the DC characteristics of the SYSCLK and

SYSCLK# signals.

VCROSS

VThreshold-DC = 400mV

VThreshold-AC = 450mV

Figure 11. SYSCLK and SYSCLK# Differential Clock Signals

Chapter 8

Electrical Data

37

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AMD 8 manual SYSCLK and SYSCLK# DC Characteristics, Preliminary Information, Chapter, Electrical Data