AMD manual SYSCLK Waveform, Preliminary Information, AMD Athlon XP Processor Model 8 Data Sheet

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet 25175H— March 2003

7.2Advanced 333 FSB AMD Athlon™ XP Processor Model 8 SYSCLK and SYSCLK# AC Characteristics

Table 6 shows the SYSCLK/SYSCLK# differential clock AC characteristics of this processor.

Table 6.	SYSCLK and SYSCLK# AC Characteristics
Symbol		Parameter Description	Minimum	Maximum	Units	Notes
		Clock Frequency	50	166	MHz	1
		Duty Cycle	30%	70%
t1		Period	6		ns	2, 3
t2		High Time	1.0		ns
t3		Low Time	1.0		ns
t4		Fall Time		2	ns
t5		Rise Time		2	ns
		Period Stability		± 300	ps
Notes:
1. The AMD Athlon™ system bus operates at twice this clock frequency.
2. Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL
to track the jitter. The –20dB attenuation point, as measured into a 20- or 30-pF load must be less than 500 kHz.
3. Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread
spectrum clock generators). In no cases can the AMD Athlon system bus period violate the minimum specification above.
AMD Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a
maximum rate of 100 kHz.

Figure 9 shows a sample waveform of the SYSCLK signal.

	t2
VCROSS	VThreshold-AC	t3
	t	t4
	5
		t1

Figure 9. SYSCLK Waveform

28 Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications Chapter 7