AMD manual Preliminary Information, AMD Athlon XP Processor Model 8 Data Sheet

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet 25175H— March 2003

Power-Up Timing Requirements. The signal timing requirements are as follows:

1.RESET# must be asserted before PWROK is asserted.

The AMD Athlon XP processor model 8 does not set the correct clock multiplier if PWROK is asserted prior to a RESET# assertion. It is recommended that RESET# be asserted at least 10 nanoseconds prior to the assertion of

PWROK.

In practice, a Southbridge asserts RESET# milliseconds before PWROK is asserted.

2.All motherboard voltage planes must be within specification before PWROK is asserted.

PWROK is an output of the voltage regulation circuit on the

motherboard. PWROK indicates that VCC_CORE and all other voltage planes in the system are within specification.

The motherboard is required to delay PWROK assertion for a minimum of three milliseconds from the 3.3 V supply being within specification. This delay ensures that the system clock (SYSCLK/SYSCLK#) is operating within specification when PWROK is asserted.

The processor core voltage, VCC_CORE, must be within specification as dictated by the VID[4:0] pins driven by the processor before PWROK is asserted. Before PWROK assertion, the AMD Athlon processor is clocked by a ring oscillator.

The processor PLL is powered by VCCA. The processor PLL does not lock if VCCA is not high enough for the processor logic to switch for some period before PWROK is asserted. VCCA must be within specification at least five microseconds before PWROK is asserted.

In practice VCCA, VCC_CORE, and all other voltage planes must be within specification for several milliseconds before PWROK is asserted.

After PWROK is asserted, the processor PLL locks to its operational frequency.

3.The system clock (SYSCLK/SYSCLK#) must be running before PWROK is asserted.

When PWROK is asserted, the processor switches from driving the internal processor clock grid from the ring oscillator to driving from the PLL. The reference system

46 Signal and Power-Up Requirements Chapter 9