AMD 8 manual Detailed Pin Descriptions, See the AMD Athlon System Bus Specification, order#

Models: 8

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11.3Detailed Pin Descriptions

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H— March 2003

11.3Detailed Pin Descriptions

 

The information in this section pertains to Table 25 on page 66.

A20M# Pin

A20M# is an input from the system used to simulate address

 

wrap-around in the 20-bit 8086.

AMD Pin

AMD Socket A processors do not implement a pin at location

 

AH6. All Socket A designs must have a top plate or cover that

 

blocks this pin location. When the cover plate blocks this

 

location, a non-AMD part (e.g., PGA370) does not fit into the

 

socket. However, socket manufacturers are allowed to have a

 

contact loaded in the AH6 position. Therefore, motherboard

 

socket design should account for the possibility that a contact

 

could be loaded in this position.

AMD Athlon™

See the AMD Athlon™ System Bus Specification, order# 21902

System Bus Pins

for information about the system bus pins — PROCRDY,

 

PWROK, RESET#, SADDIN[14:2]#, SADDINCLK#,

 

SADDOUT[14:2]#, SADDOUTCLK#, SDATA[63:0]#,

 

SDATAINCLK[3:0]#, SDATAINVALID#, SDATAOUTCLK[3:0]#,

 

SDATAOUTVALID#, SFILLVALID#.

Analog Pin

Treat this pin as a NC.

APIC Pins, PICCLK,

The Advanced Programmable Interrupt Controller (APIC) is a

PICD[1:0]#

feature that provides a flexible and expandable means of

 

delivering interrupts in a system using an AMD processor. The

 

pins, PICD[1:0], are the bi-directional message-passing signals

 

used for the APIC and are driven to the Southbridge or a

 

dedicated I/O APIC. The pin, PICCLK, must be driven with a

 

valid clock input.

 

For more information, see Table 19, “APIC Pin AC and DC

 

Characteristics,” on page 44.

CLKFWDRST Pin

CLKFWDRST resets clock-forward circuitry for both the system

 

and processor.

CLKIN, RSTCLK

Connect CLKIN with RSTCLK and name it SYSCLK. Connect

(SYSCLK) Pins

CLKIN# with RSTCLK# and name it SYSCLK#. Length match

 

the clocks from the clock generator to the Northbridge and

 

processor.

 

See “SYSCLK and SYSCLK#” on page 79 for more information.

74

Pin Descriptions

Chapter 11

Page 86
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AMD 8 manual Detailed Pin Descriptions, See the AMD Athlon System Bus Specification, order#, Preliminary Information