Analog Devices ADSP-21020 manual Output disable time tDIS is the difference between

ADSP-21020

TEST CONDITIONS

Output Disable Time

Output pins are considered to be disabled when they stop driving, go into a high-impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by ΔV is dependent on the capacitive load, CL, and the load current, IL. It can be approximated by the following equation:

tDECAY = CL ΔV

IL

The output disable time (tDIS) is the difference between

tMEASURED and tDECAY as shown in Figure 13. The time tMEASURED) is the interval from when the reference signal switches to when the output voltage decays ΔV from the

measured output high or output low voltage. tDECAY is calculated with ΔV equal to 0.5 V, and test loads CL and IL.

Output Enable Time

Output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate tDECAY using the above equation. Choose ΔV to be the difference between the ADSP-21020’s output voltage and

the input threshold for the device requiring the hold time. A typical ΔV will be 0.4 V. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per

data line). The hold time will be tDECAY plus the minimum disable time (i.e. tHDWD for the write cycle).

IOL

TO

OUTPUT +1.5V PIN

50pF*

IOH

*AC TIMING SPECIFICATIONS ARE CALCULATED FOR 100pF DERATING ON THE FOLLOWING PINS: PMA23–0,PMS1–0,PMRD,

PMWR, PMPAGE, DMA31–0, DMS3–0, DMRD, DMWR, DMPAGE

Figure 14. Equivalent Device Loading For AC Measurements (Includes All Fixtures)

INPUT OR 1.5V 1.5V

OUTPUT

Figure 15. Voltage Reference Levels For AC Measurements (Except Output Enable/Disable)

REFERENCE
SIGNAL
	t MEASURED
t DIS		tENA
VOH (MEASURED)		VOH (MEASURED)
	VOH (MEASURED) –ΔV	2.0V
OUTPUT
	VOL (MEASURED) +ΔV	1.0V
VOL (MEASURED)		VOL (MEASURED)

tDECAY

OUTPUT STOPS DRIVING	HIGH-IMPEDANCE STATE. TEST CONDITIONS	OUTPUT STARTS DRIVING
	CAUSE THIS VOLTAGE LEVEL TO BE
	APPROXIMATELY 1.5 V.

Figure 13. Output Enable/Disable

–24– REV. C