Ordering Guide | Analog Devices ADSP-21020 specification

ADSP-21020

	ORDERING GUIDE

	Ambient Temperature	Instruction	Cycle Time
Part Number*	Range	Rate (MHz)	(ns)	Package

ADSP-21020KG-80	0°C to +70°C	20	50	223-Lead Ceramic Pin Grid Array
ADSP-21020KG-100	0°C to +70°C	25	40	223-Lead Ceramic Pin Grid Array
ADSP-21020KG-133	0°C to +70°C	33.3	30	223-Lead Ceramic Pin Grid Array	C1601c–5–8/94
ADSP-21020BG-80	–40°C to +85°C	20	50	223-Lead Ceramic Pin Grid Array	C1601c–5–8/94
ADSP-21020BG-100	–40°C to +85°C	25	40	223-Lead Ceramic Pin Grid Array
ADSP-21020BG-120	–40°C to +85°C	30	33.3	223-Lead Ceramic Pin Grid Array
ADSP-21020TG-80	–55°C to +125°C	20	50	223-Lead Ceramic Pin Grid Array
ADSP-21020TG-100	–55°C to +125°C	25	40	223-Lead Ceramic Pin Grid Array
ADSP-21020TG-120	–55°C to +125°C	30	33.3	223-Lead Ceramic Pin Grid Array
ADSP-21020TG-80/883B	–55°C to +125°C	20	50	223-Lead Ceramic Pin Grid Array
ADSP-21020TG-100/883B	–55°C to +125°C	25	40	223-Lead Ceramic Pin Grid Array
ADSP-21020TG-120/883B	–55°C to +125°C	30	33.3	223-Lead Ceramic Pin Grid Array

*G = Ceramic Pin Grid Array.

PRINTED IN U.S.A.

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REV. C

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Analog Devices ADSP-21020 manual Ordering Guide

Contents

ADSP-21020 ADSP-21020 Address Generators and Program Sequencer Interrupts Pin Name Type Function Reset DmpageDmts Clkiin Compute If conditionIf condition Compute DMIa, Mb = dreg Name Description Notation MeaningItalics Fixed-Point Floating-Point MRF MRB = MRF = MRB MRF = MRF = SAT MRF = SAT MRB= MRB MRF = MRF = RND MRF = RND MRB Shifter Shifter Immediate Fixed-Point Vector Address Hex FunctionIRQ3 IRQ2 Grade Parameter Min Max Unit Parameter Test Conditions Min Max Unit Reset Setup before Clkin High 29 + DT/2 Timing RequirementClkin Period 150 Clkin Width High TDTEX Clkin High to Timexp Hold after Clkin HighPulse Width TCK + FLAG3-0INSetup before Clkin High 19 + 5DT/16 FLAG3-0OUTDelay from Clkin HighClkin High to FLAG3-0OUTEnable Clkin High to FLAG3-0OUTDisable Memory Interface Disable to Low Clkin High to Memory Interface Enable 25 + DT/2Timing Requirement Hold after Clkin High Setup before Clkin High 14 + DT/4 XTS Delay after Address, Select 28 + 7DT/8XTS Delay after Low 16 + DT/2 Switching Characteristic XACK Delay from Address + 7DT/8 XACK Delay from XRD Low + DT/2XACK Setup before Clkin High + DT/4 XACK Hold after Clkin High Switching Characteristic Memory Read XACK Delay from Address, Select 27 + 7DT/8 XACK Delay from XWR Low 15 + DT/2Data Setup before XWR High + DT/2 Data Disable before XWR XRD Low + 3DT/8 Memory Write TDI, TMS Setup before TCK High System Inputs Setup before TCK HighPulse Width 200 160 132 120 Switching Characteristic TDO Delay from TCK Low Ieee 1149.1 Test Access Port Output disable time tDIS is the difference between Output Enable/Disable Capacitive Loading Type Pins Switch ExamplePin Ptotal = Pext + 5 V 3 Iddin typ = 0.210 + 1.15 = 1.36 W 3 0.1 inches Bottom View Ribbon Cable ADSP-21020 ADSP-21020 PGA PIN Location Name Inches Millimeters Symbol MIN MAX Ordering Guide