Capacitive Loading
Output delays are based on standard capacitive loads: 100 pF on address, select, page and strobe pins, and 50 pF on all others (see Figure 14). For different loads, these timing parameters should be derated. See the Hardware Configuration chapter of the
Figures 16 and 17 show how the output rise time varies with capacitance. Figures 18 and 19 show how output delays vary with capacitance. Note that the graphs may not be linear outside the ranges shown.
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| 9.18 |
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2.0V) | 8 |
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– |
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(0.8V | 6 |
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– ns | 5 |
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| 3.95 |
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TIME | 4 |
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RISE | 3 |
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2 |
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| 0 |
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| LOAD CAPACITANCE – pF |
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NOTES:
(1)OUTPUT PINS BG, TIMEXP
(2)OUTPUT PINS
Figure 16. Typical Output Rise Time vs. Load Capacitance (at Maximum Case Temperature)
2.0V) | 4 |
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| 3.59 |
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(0.8V | 3 |
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– ns |
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| 3.00 |
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2 |
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TIME | 1.33 |
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RISE | 1 | 0.85 |
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| π |
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| 25 | 50 | 75 | 100 | 125 | 150 | 175 | 200 |
LOAD CAPACITANCE – pF
NOTES:
(1)OUTPUT PINS
(2)OUTPUT PINS PMRD, PMWR, DMRD, DMWR
Figure 17. Typical Output Rise Time vs. Load Capacitance (at Maximum Case Temperature)
ADSP-21020
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| 11.19 |
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– ns | 10 |
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HOLDOR | 8 |
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DELAY |
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| 1 |
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6 |
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| 5.34 |
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OUTPUT |
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4 |
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NOMINAL |
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LOAD CAPACITANCE – pF
NOTES:
(1)OUTPUT PINS BG, TIMEXP
(2)OUTPUT PINS
Figure 18. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature)
– ns | 3 |
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| 2.99 |
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| 1 |
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HOLD | 2 |
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| 2.27 |
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OR | 1 |
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DELAY | NOMINAL |
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OUTPUT | – 1.70 |
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| – 2.24 |
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| 25 | 50 | 75 | 100 | 125 | 150 | 175 | 200 |
LOAD CAPACITANCE – pF
NOTES:
(1)OUTPUT PINS
(2)OUTPUT PINS PMRD, PMWR, DMRD, DMWR
Figure 19. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature)
REV. C |