60
4929B–AUTO–01/07
ATA6264 [Preliminary]
Table 18-1. Electrical Characteristics – Voltage/Current Sources (IASGx Sources)
No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*
17.1 Output voltage (V1)
(x = 1 to 5),
–40 mA < IIASGx < –0.5mA
VISENS = 0.96 ×VVPERI
IASGxV1IASGx –6% 10 +6% V A
17.2 Output voltage (V2)
(x = 1 to 5),
–40 mA < IIASGx < –0.5mA
VISENS = 0.96 ×VVPERI
IASGx switched to 5V
VEVZ > 11V
IASGxV2IASGx –6% 5 +6% V A
17.2a Output voltage (V2)
(x = 1 to 5),
–25 mA < IIASGx < –0.5mA
VISENS = 0.96 ×VVPERI
IASGx switched to 5V
VEVZ > 9V to 11V
IASGxV2IASGx –6% 5 +6% V A
17.3
Output voltage overshoot at
IASGx due to regulator
characteristic
(x = 1 to 5)
when IASG = 5V
when IASG = 10V
IASGxVIASGx 5.9
11.3
V
V
A
A
17.4 Maximum duration of voltage
overshoot at IASGx
(x = 1 to 5),
with VIASGx = 10V / 0.5 mA <
RLOAD < VIASGx = 5V / 40mA
IASGxtIASGx 30 µs A
17.5 Linear range for current mirror
at IASGx
(x = 1 to 5),
0V = VISENS = 0.96 ×VPERI IASGxIIASGx –40 –0.5 mA A
17.6 Internal current limitation at
IASGx(x = 1 to 5) IASGxIIASGx –150 –50 mA A
17.7 Current ratio #1
(x = 1 to 5),
CR1x = IIASGx / IISENS
0V = VISENS = 0.96 ×VVPERI
–40 mA < IIASGx< –0.5mA
IASGxCR1x –3% 9.9 +3% A
17.8 Current ratio #2
(x = 1 to 5),
CR2x = IIASGx /I
ISENS
0V = VISENS = 0.96 ×VVPERI
–40 mA < IIASGx < –0.5mA
IASGxCR2x –3% 14.9 +3% A
17.9 Settling time
(x = 1 to 5),
RIASGx = 250, no capacitive
load at IASGx
ISENSE tISENSE 050µsA
17.10 Switch-on delay
(x = 1 to 5)
Measured from rising edge
of SSQ to
VIASGx = 0.1 ×VIASGx
RIASGx= 250, no
capacitive load at IASGx
IASGxtIASGx 050µsA
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter