69
4929B–AUTO–01/07
ATA6264 [Preliminary]
21.7 Time from SSQ falling edge to
MISO MSB valid (2) MISO tMISOMSB_V 0 400 ns A
21.8 Time from SCLK rising edge to
MISO valid (2) MISO tMISOV 040nsA
21.9 Time from SSQ rising edge to
MISO tristate condition (2) MISO tMISOhiZ 040nsA
21.10 No-data time between serial
interface commands tnodata 1.5 µs A(3)
21.11 Clock frequency CLK fSCLK 08MHzA
(3)
21.12 Pull-up current VPERI SSQ Rpu_SSQ –95 –45 µA A
21.13 Pull-up current VPERI SCLK Rpu_SCLK –95 –45 µA A
21.14 SCLK high/low time SCLK tCL 40 ns A(3)
21.15 Input voltage high level SSQ, SCLK,
MOSI VH0.5 ×
VVPERI A
21.16 Input voltage low level SSQ, SCLK,
MOSI VL0.25 ×
VVPERI A
21.17 Input voltage hysteresis SCLK VHYS 50 250 mV A
21.18 Output voltage high level IMISO = –1 mA to 0 mA MISO VHVVPERI
– 0.8 VVPERI VA
21.19 Output voltage low level IMISO = 0 mA to 1 mA MISO VL00.4VA
21.20 Output current high level driven
to short circuit VVPERI = 5V MISO IMISO –47 –10 mA A
21.21 Output current low level sinking
from VPERI level VVPERI = 5V MISO IMISO 645mAA
21.22 Input capacitance SSQ, SCLK,
MOSI CIN 10 pF D
21.23 Output capacitance Switched-off condition MISO CMISO 10 pF D
21.24 Leakage current Switched-off condition MISO IMISO –10 +10 µA A
21.25
Number of clock cycles to be
detected between falling and
rising edge of SSQ, to set error
signal in status register to “0”
16 16 A
Table 22-1. Electrical Characteristics (Continued)– SerialInterface Commands
No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Voltage levels for serial interface timing measurements: High level = 0.7 × VVPERI, low level = 0.2 × VVPERI
2. Timing specified with a 100-pF external load at pin MISO
3. System requirement