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Figure 3.9 SHARC Pinout
The time allotted for the SHARC to process this audio data is 330us (16 samples x
• A/D Conversion | 667us |
• 5x "brick" delay | 1667us |
• DAC Conversion | 520us |
• Total Delay | 2854us |
This delay is constant and not dependent upon the particular processing being done.
SDRAM provides a high speed synchronous memory resource. Only the four SHARC processors have ac- cess to SDRAM and they are responsible for the ac- cess and maintenance of it. Each SHARC monitors the
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Circuit Theory