Features
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Functional Description
Logic Block Diagram
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Dual-Ported
Figure 1. 144-Ball BGA Top View
Pin Configurations
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
CY7C0837AV / CY7C0830AV / CY7C0831AV / CY7C0832AV / CY7C0833AV
Figure 2. 120-Pin Thin Quad Flat Pack TQFP Top View
Pin Configurations
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
CY7C0830AV / CY7C0831AV / CY7C0832AV / CY7C0832BV
Pin Definitions
Byte Select Operation
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Mailbox Interrupts
Master Reset
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Address Counter and Mask Register Operations
Counter Increment Operation
Counter Reset Operation
Counter Load Operation
Counter Hold Operation
Mask Readback Operation
Mask Reset Operation
Retransmit
Counting by Two
Figure 3. Counter, Mask, and Mirror Logic Block Diagram
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
CY7C0831AV, CY7C0832AV
Performing a TAP Reset
CY7C0837AV, CY7C0830AV
CY7C0832BV, CY7C0833AV
Bypass
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Instruction
Identification
Operating Range
Electrical Characteristics
Maximum Ratings
Capacitance
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Switching Characteristics
b Three-state Delay Load
a Normal Load Load
Switching Characteristics continued
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
29. Test conditions used are Load
JTAG Timing and Switching Waveforms
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
CY7C0831AV, CY7C0832AV
Switching Waveforms
CY7C0837AV, CY7C0830AV
CY7C0832BV, CY7C0833AV
CY7C0831AV, CY7C0832AV
Switching Waveforms continued
CY7C0837AV, CY7C0830AV
CY7C0832BV, CY7C0833AV
CY7C0831AV, CY7C0832AV
Switching Waveforms continued
CY7C0837AV, CY7C0830AV
CY7C0832BV, CY7C0833AV
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Switching Waveforms continued
Figure 15. Counter Reset40
Figure 14. Write with Address Counter Advance39
+ Feedback
Switching Waveforms continued
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
AnAn+1
Figure 17. LeftPort LPort Write to RightPort RPort Read47, 48
Switching Waveforms continued
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
+ Feedback
Figure 18. Counter Interrupt and Retransmit 15, 42, 50, 51, 52
Switching Waveforms continued
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
+ Feedback
CY7C0831AV, CY7C0832AV
Switching Waveforms continued
CY7C0837AV, CY7C0830AV
CY7C0832BV, CY7C0833AV
256K ×
Ordering Information
512K × 18 9M 3.3V Synchronous CY7C0833AV Dual-Port SRAM
18 4M 3.3V Synchronous CY7C0832AV/CY7C0832BV Dual-Port SRAM
CY7C0837AV, CY7C0830AV
Package Diagrams
32K × 18 512K 3.3V Synchronous CY7C0837AV Dual-Port SRAM
CY7C0831AV, CY7C0832AV
Figure 21. 120-Pin Thin Quad Flatpack 14 x 14 x 1.4 mm
Package Diagrams
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Page 26 of
Document Number
Document History Page
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
ECN No
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