Cypress CY7C0833AV, CY7C0837AV, CY7C0832BV, CY7C0830AV, CY7C0832AV Logic Block Diagram, Dual-Ported

CY7C0837AV, CY7C0830AV

CY7C0831AV, CY7C0832AV

CY7C0832BV, CY7C0833AV

Logic Block Diagram [2]

OEL			OER
R/WL		R/WR
	L			R
B0			B0
	L			R
B1			B1

CE0L	CE0R
CE1L	CE1R

DQ9L–DQ17L	9	I/O	I/O		9
		Control	Control			DQ9R–DQ17R
	9			9
DQ0L–DQ8L						DQ0R–DQ8R

.

True

Dual-Ported

RAM Array

19

19

A0L–A18L

Mask Register

Mask Register

A0R–A18R

R

CNT/MSK

L

CNT/MSK

ADS

L

Counter/

Counter/

ADS

Address

Address

Address

Address

CNTEN

CNTENL

Register

Decode

Decode

Register

R

CNTRST

CNTRST

CLKL

L

Mirror Reg

Mirror Reg

CLKR

L

CNTINT

R

CNTINT

TMS

Reset

TDO

Interrupt

MRST

TDI

JTAG

Interrupt

INTL

Logic

INTR

Logic

TCK

Logic

Note

2.CY7C0837AV has 15 address bits, CY7C0830AV has 16 address bits, CY7C0831AV has 17 address bits, CY7C0832AV/CY7C0832BV has 18 address bits and CY7C0833AV has 19 address bits.

Document #: 38-06059 Rev. *S Page 2 of 28

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