Cypress manual Switching Waveforms continued, CY7C0837AV, CY7C0830AV, CY7C0831AV, CY7C0832AV

						CY7C0837AV, CY7C0830AV
						CY7C0831AV, CY7C0832AV
						CY7C0832BV, CY7C0833AV
Switching Waveforms (continued)
		Figure 10. Bank Select Read[34, 35]
	tCYC2
	tCH2	tCL2
CLK
	tSA	tHA
ADDRESS(B1)	A0	A	A		A3	A4		A5
		1	2
	tSC	tHC
CE(B1)
		tCD2	tSC tHC	tCD2		tCKHZ	tCD2	tCKHZ
DATA			Q0		Q1			Q3
OUT(B1)		tHA
	t		t		t		t
	SA
			DC		DC		CKLZ
ADDRESS	A	A	A		A3	A4		A5
(B2)	0	1	2
		tSC		tHC
CE(B2)
	t	t				tCD2	tCKHZ	tCD2
DATAOUT(B2)	SC	HC
						Q		Q4
						2
					tCKLZ			tCKLZ
	Figure 11. Read-to-Write-to-Read (OE = LOW)[33, 36, 37, 38, 39]
	t	tCYC2t
	CH2	CL2
CLK
CE
	tSC	tHC
		tSW	tHW
R/W	tSW	tHW
ADDRESS	An	An+1	An+2		An+2	An+3		An+4
					tSD tHD
	tSA	tHA
DATAIN		tCD2	tCKHZ		Dn+2			tCD2
		Qn						Q
DATAOUT								n+3
							tCKLZ
		READ	NO OPERATION			WRITE	READ

Notes

34.In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx18 device from this data sheet. ADDRESS(B1) = ADDRESS(B2).

35.ADS = CNTEN= BE0 – BE1 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.

36.Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.

37.During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.

38.CE0 = OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.

39.CE0 = BE0 – BE1 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, because OE = LOW, the Write operation cannot be completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.

Document #: 38-06059 Rev. *S Page 17 of 28

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