Cypress CY7C0837AV, CY7C0830AV, CY7C0831AV, CY7C0832AV, CY7C0832BV, CY7C0833AV, DQ0 - DQ17

					CY7C0837AV, CY7C0830AV
					CY7C0831AV, CY7C0832AV
					CY7C0832BV, CY7C0833AV
Switching Waveforms (continued)
		Figure 19. MailBox Interrupt Timing [54, 55, 56, 57, 58]
	tCYC2
tCH2	tCL2
CLKL
	tSA	tHA
L_PORT	7FFFF		An	An+1	An+2	An+3
ADDRESS
			tSINT

INT R tRINT

tCYC2

tCH2 tCL2

CLKR

tSA

tHA

R_PORT	Am	Am+1	7FFFF	Am+3	Am+4
ADDRESS

Table 7. Read/Write and Enable Operation (Any Port) [2, 17, 59, 60, 61]

			Inputs				Outputs	Operation
OE	CLK			CE0	CE1	R/W	DQ0 – DQ17
X				H	X	X	High-Z	Deselected
X				X	L	X	High-Z	Deselected
X				L	H	L	DIN	Write
L				L	H	H	DOUT	Read
H		X		L	H	X	High-Z	Outputs Disabled

Notes

54.CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.

55.Address “7FFFF” is the mailbox location for R_Port of the 9Mb device.

56.L_Port is configured for Write operation, and R_Port is configured for Read operation.

57.At least one byte enable (BE0 – BE1) is required to be active during interrupt operations.

58.Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.

59.OE is an asynchronous input signal.

60.When CE changes state, deselection and Read happen after one cycle of latency.

61.CE0 = OE = LOW; CE1 = R/W = HIGH.

Document #: 38-06059 Rev. *S Page 23 of 28

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