FUNCTIONAL | DESCRIPTION |
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| A . INTERRUPT | ENABLE | REGISTER | |||
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D7 | 0 |
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D6 | 0 |
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D5 | 0 |
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D4 | 0 |
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D3 | EDSSI | MODEM status | ||||
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D2 | ELSI | Receiver | line status | |||
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D1 | ETBEI | Transmitter holding register empty | ||||
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D0 | ERBFI | Received | data available | |||
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Figure 3. Interrupt enable register bit definitions. | ||||||
EDSSI | - | MODEM | Status | Interrupt: | ||
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| When set (logic 1), enables interrupt on clear to | ||||
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| send, data set ready, ring indicator, and data | ||||
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| carrier | detect. |
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ELSI | - | Receiver | Line Status | Interrupt: | ||
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| When set (logic 1), enables interrupt on overrun, | ||||
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| parity, and framing errors, and break indication. | ||||
ETBEI | - | Transmitter | Holding Register Empty Interrupt: | |||
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| W h e n s e t ( l o g i c 1 ) , e n a b l e s i n t e r r u p t o n | ||||
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| transmitter | register | empty. | ||
ERBFI | - | Received | Data Available Interrupt: | |||
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| When set (logic 1), enables interrupt on received | ||||
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| data | available or FIFO trigger level. |
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