B
AUD RATE SELECTION
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1 | o | o+ o | 4 |
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2 | o | o+ o | 5 |
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(a) ÷1 | input | clock | (b) | ÷2 | input | clock |
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1 | o | o | 4 |
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2 | o | o | 5 |
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(c) ÷5 | input | clock | (d) | ÷10 | input | clock |
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F i g u r e 1 4 . | I n p u t c l o c k f r e q u e n c y o p t i o n s . | F o r | ||||||||||
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| compatibility, | the | jumper |
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| ÷10 | ( | 18.432 | MHz | ÷ | 10 | = 1.8432 MHz ). |
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T h e b a u d r a t e m a y n o w b e c a l c u l a t e d u s i n g t h e | ||||||||||||
equation |
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| crystal frequency |
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| baud rate | = |
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| 16 x divider x DL |
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where
divider = the clock divider setting of jumper J1 DL = the value programmed into the baud rate
divisor latches of the 16550.
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Desired | Divisor | Error Between Desired | ||||
Baud Rate | Latch Value | and Actual Value (%) | ||||
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110 | 1047 | 0.026 | ||||
300 | 384 | - | ||||
1200 | 96 | - | ||||
2400 | 48 | - | ||||
4800 | 24 | - | ||||
9600 | 12 | - | ||||
19200 | 6 | - | ||||
38400 | 3 | - | ||||
56000 | 2 | 2.86 | ||||
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Figure 15 . Divisor latch settings for common baud rates using a 1.8432 MHz input clock.
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