FUNCTIONAL DESCRIPTION
Bits BI, FE, PE, and OE are the sources of receiver line status interrupts. The bits are reset by reading the line status register . In FIFO mode, these bits are associated with a specific character in the FIFO and the exception is revealed only when that character reaches the top of the FIFO.
BI | - | Break | Interrupt: |
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| Indicates the receive data input has been in the | |||||||||
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| spacing state (logic 0) for longer | than | one | full | ||||||
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| word | transmission | time. |
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| FIFO | mode: |
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| Only | one | zero character is loaded into the FIFO | |||||||
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| and | transfers are disabled | until SIN goes to | the | ||||||
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| m a r k s t a t e ( l o g i c 1 ) a n d a v a l i d s t a r t b i t i s | |||||||||
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| received. |
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FE | - | Framing Error: |
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| Indicates the received character had an invalid | |||||||||
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| stop | bit. | The | stop | bit following | the | last | data | ||
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| or parity bit was | a 0 | bit (spacing level). |
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PE | - | Parity Error: |
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| Indicates | that | the | received | data | does | not | have | ||
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| the | correct parity. |
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OE | - | Overrun Error: |
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| Indicates | the receive buffer was not read before | ||||||||
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| the | next | character was received and the | character | ||||||
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| is destroyed. |
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| FIFO | mode: |
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| Indicates | the FIFO is full and another character | ||||||||
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| has been shifted in. The character in the shift | |||||||||
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| register | is destroyed but | is | not | transferred to | |||||
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| the | FIFO. |
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DR | - | Data ready: |
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| Indicates | data | is present | in | the | receive buffer | ||||
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| o r F I F O . | D R i s r e s e t b y r e a d i n g t h e r e c e i v e | ||||||||
buffer register or receiver FIFO.
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