IBM DS-2000 I. Introduction, Ii . Board Description, t h e I B M P C / X T / A T m o d e l s

I. INTRODUCTION

The DS-2000 is a dual channel asynchronous serial c o m m u n i c a t i o n a d a p t e r w h i c h u t i l i z e s b a l a n c e d differential drivers and receivers to provide RS - 422 - A communications. It is capable of reliable communications

over long distances (4000 feet) within	noisy industrial
e n v i r o n m e n t . D a t a i s c o m m u n i c a t e d	t h r o u g h t w o D - 9

c o n n e c t o r s w h i c h	p r o v i d e s h i e l d i n g f r o m e n v i r o n m e n t a l
noise . Optional	high speed transient suppressers may
also be installed on the DS - 2000 to further reduce the
effects of environmental signal transients and surges.

The serial interface is		accomplished through a pair
of 16550	Asynchronous Communication Elements (ACEs). The
16550 is	compatible with the	8250	and	16450 ACEs used in
t h e I B M P C / X T / A T m o d e l s .		T h e 1 6 5 5 0 a l s o h a s a n
additional FIFO mode that reduces			CPU	overhead	at higher
data rates.
The	DS-2000 supports sixteen		base	addresses	for each

A C E t h r o u g h t h e P r o g r a m m a b l e O p t i o n S e l e c t ( P O S )

including	the eight		addresses	designated SERIAL 1 through
S E R I A L 8 .		T h e a d d r e s s e s		a r e i n d e p e n d e n t f o r e a c h
channel.	CPU interrupt level			selections are also handled
t h r o u g h t h e P O S .			E a c h c h a n n e l m a y s e l e c t a s e p a r a t e
interrupt	or	share an	interrupt	level with other devices.

II. BOARD DESCRIPTION

A c o m p o n e n t d i a g r a m o f t h e D S - 2 0 0 0 s h o w i n g t h e

locations of	the 16550	ACEs, configuration	jumpers, and
D - 9 c o n n e c t o r s i s s h o w n i n f i g u r e 1 .			T h e f i r s t
communication	channel is	controlled by the	16550 labeled

U 9 , j u m p e r J 2 , a n d i s a c c e s s e d t h r o u g h t h e c o n n e c t o r labeled CN1. The second channel uses the 16550 labeled U10, jumper J3, and is accessed through the connector labeled CN2. The clock rate divider for both channels is controlled by jumper J1.

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