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| FUNCTIONAL DESCRIPTION |
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RRST | - | Receive FIFO Reset: |
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| W h e n s e t ( l o g i c 1 ) , a l l b y t e s i n t h e r e c e i v e r | |||
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| FIFO are cleared | and the counter | is reset. | The |
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| s h i f t r e g i s t e r i s n o t c l e a r e d . | R R S T i s s e l f - | ||
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| clearing. |
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FE | - | FIFO Enable: |
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| W h e n s e t ( l o g i c 1 ) , e n a b l e s t r a n s m i t t e r a n d | |||
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| r e c e i v e r F I F O s . | W h e n c l e a r e d ( l o g i c 0 ) , a l l | ||
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| bytes in both FIFOs are cleared. | This bit | must | |
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| b e s e t w h e n o t h e r b i t s i n t h e F I F O c o n t r o l | |||
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| r e g i s t e r a r e w r i t t e n t o o r t h e b i t s w i l l b e | |||
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| ignored. |
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D . LINE CONTROL | REGISTER |
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| + |
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D7 | DLAB | Divisor latch | access bit | |||||
| + |
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D6 | BKCN | Break |
| control |
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| + |
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D5 | STKP | Stick |
| parity |
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| + |
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D4 | EPS | Even | parity select | |||||
| + |
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D3 | PEN | Parity | enable |
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| + |
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D2 | STB | Number | of stop | bits | ||||
| + |
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D1 | WLS1 | + |
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| + | Word | length select | |||||
D0 | WLS0 | + |
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| + |
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Figure 8. Line Control Register bit definitions.
DLAB - Divisor Latch Access Bit:
DLAB | must be | set to logic 1 to access the baud |
rate | divisor | latches. DLAB must be set to logic |
0 t o a c c e s s t h e r e c e i v e r b u f f e r , t r a n s m i t t i n g | ||
holding register and interrupt enable register. | ||
BKCN - Break | Control: |
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When set (logic 1), the serial output (SOUT) is | ||
forced to the | spacing state (logic 0). | |
iii
