FUNCTIONAL | DESCRIPTION |
III. 16550 FUNCTIONAL | DESCRIPTION |
T h e 1 6 5 5 0 i s a n u p g r a d e o f t h e s t a n d a r d 1 6 4 5 0 | |
Asynchronous Communications | Element (ACE). Designed to |
b e c o m p a t i b l e w i t h t h e 1 6 4 5 0 , t h e 1 6 5 5 0 e n t e r s t h e character mode on reset and in this mode will appear as a 16450 to user software. An additional mode, FIFO mode,
c a n b e s e l e c t e d | t o r e d u c e C P U o v e r h e a d a t h i g h d a t a |
rates. The FIFO | mode increases performance by providing |
two | internal | |||
to | buffer data | and | reduce | the number of interrupts issued |
to | the CPU. |
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Other features of | the | 16550 | include: | |
| Programmable baud rate, character length, parity, | |||
and number of stop bits |
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| Automatic addition and removal of start, stop, and | |||
parity bits |
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| Independent and prioritized transmit, receive and | |||
status interrupts |
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| Transmitter clock output to drive receiver logic | |||
| External receiver | clock | input | |
The following pages provide a brief summary of the internal registers available within the 16550 ACE. The registers are addressed as shown in figure 2 below.
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DLAB | A2 | A1 | A0 | REGISTER | DESCRIPTION | ||||||
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0 | 0 | 0 | 0 | Receive buffer | (read) |
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| Transmit holding register (write) | ||||||
0 | 0 | 0 | 1 | Interrupt | enable |
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x | 0 | 1 | 0 | Interrupt identification (read) | |||||||
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| FIFO control (write) |
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x | 0 | 1 | 1 Line control |
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x | 1 | 0 | 0 MODEM control |
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x | 1 | 0 | 1 Line status |
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x | 1 | 1 | 0 MODEM status |
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x | 1 | 1 | 1 Scratch |
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1 | 0 | 0 |
| 0 | Divisor | latch | (least | significant) | |||
1 | 0 | 0 |
| 1 | Divisor | latch | (most | significant) | |||
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Figure 2. Internal register map for 16550 ACE. DLAB is accessed through the Line Control Register.
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