CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Features
Functional Description
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Logic Block Diagram
Dual-Ported
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Pin Configurations
Figure 1. 144-Ball BGA Top View
CY7C0837AV / CY7C0830AV / CY7C0831AV / CY7C0832AV / CY7C0833AV
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Pin Configurations
Figure 2. 120-Pin Thin Quad Flat Pack TQFP Top View
CY7C0830AV / CY7C0831AV / CY7C0832AV / CY7C0832BV
Byte Select Operation
Pin Definitions
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Master Reset
Mailbox Interrupts
Address Counter and Mask Register Operations
Counter Load Operation
Counter Reset Operation
Counter Increment Operation
Counter Hold Operation
Retransmit
Mask Reset Operation
Mask Readback Operation
Counting by Two
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Figure 3. Counter, Mask, and Mirror Logic Block Diagram
CY7C0837AV, CY7C0830AV
Performing a TAP Reset
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Instruction
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Bypass
Identification
Maximum Ratings
Electrical Characteristics
Operating Range
Capacitance
b Three-state Delay Load
Switching Characteristics
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
a Normal Load Load
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Switching Characteristics continued
29. Test conditions used are Load
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
JTAG Timing and Switching Waveforms
CY7C0837AV, CY7C0830AV
Switching Waveforms
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
CY7C0837AV, CY7C0830AV
Switching Waveforms continued
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
CY7C0837AV, CY7C0830AV
Switching Waveforms continued
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Figure 15. Counter Reset40
Switching Waveforms continued
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Figure 14. Write with Address Counter Advance39
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Switching Waveforms continued
+ Feedback
AnAn+1
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Switching Waveforms continued
Figure 17. LeftPort LPort Write to RightPort RPort Read47, 48
+ Feedback
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Switching Waveforms continued
Figure 18. Counter Interrupt and Retransmit 15, 42, 50, 51, 52
+ Feedback
CY7C0837AV, CY7C0830AV
Switching Waveforms continued
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
512K × 18 9M 3.3V Synchronous CY7C0833AV Dual-Port SRAM
Ordering Information
256K ×
18 4M 3.3V Synchronous CY7C0832AV/CY7C0832BV Dual-Port SRAM
32K × 18 512K 3.3V Synchronous CY7C0837AV Dual-Port SRAM
Package Diagrams
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
Package Diagrams
Figure 21. 120-Pin Thin Quad Flatpack 14 x 14 x 1.4 mm
Page 26 of
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV
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