Cypress CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV, Counter Reset40

CY7C0837AV, CY7C0830AV

CY7C0831AV, CY7C0832AV

CY7C0832BV, CY7C0833AV

Switching Waveforms (continued)

Figure 14. Write with Address Counter Advance[39]

tCYC2

tCH2 tCL2

CLK

tSA tHA

ADDRESSAn

INTERNAL	An	An+1	An+2	An+3	An+4
ADDRESS

tSAD tHAD

ADS

CNTEN

tSCN tHCN

DATA	Dn	Dn+1	Dn+1	Dn+2	Dn+3	Dn+4
IN

tSD			tHD
	WRITE EXTERNAL			WRITE WITH	WRITE COUNTER	WRITE WITH COUNTER
		ADDRESS		COUNTER	HOLD

Figure 15. Counter Reset[40, 41]

		tCYC2
		tCH2	tCL2
CLK
						tSA	tHA
ADDRESS					An		Am		Ap
INTERNAL	Ax			0	1	An		Am	Ap
ADDRESS
			tSW	tHW
R/W
ADS
CNTEN
	tSRST	tHRST
CNTRST
			tSD	tHD
DATAIN			D0		tCD2	tCD2

DATAOUT [42]

Q

Q

Q

n

0

1

COUNTER

WRITE

tCKLZ

READ

READ

READ

READ

RESET

ADDRESS 0

ADDRESS 0

ADDRESS 1

ADDRESS An

ADDRESS Am

Notes

40.CE0 = BE0 – BE1 = LOW; CE1 = MRST = CNT/MSK = HIGH.

41.No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.

42.Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.

Document #: 38-06059 Rev. *S Page 19 of 28

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