Cypress CY7C0832AV, CY7C0837AV manual Ieee 1149.1 Serial Boundary Scan Jtag, Performing a TAP Reset

										CY7C0837AV, CY7C0830AV
										CY7C0831AV, CY7C0832AV
										CY7C0832BV, CY7C0833AV
Figure 4. Programmable Counter-Mask Register Operation [2, 20]
Example:	CNTINT
Load
Counter-Mask	H	0		0	0s		0	1	1	1	1	1		1
Register = 3F
		216		215		26	25	24	23	22	21		20		Mask
				Masked Address				Unmasked Address							Register
															bit-0
Load
Address	H	X		X	Xs		X	0	0	1	0	0		0
Counter = 8
		216		215		26	25	24	23	22	21		20		Address
Max															Counter
	L	X X			Xs		X	1	1	1	1	1		1	bit-0
Address
Register
		216		215		26	25	24	23	22	21		20
Max + 1
Address	H	X		X	Xs		X	0	0	1	0 0		0
Register
		216	215			26	25	24	23	22	21		20

IEEE 1149.1 Serial Boundary Scan (JTAG) [21]

The FLEx18 family devices incorporate an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 compliant TAPs. The TAP operates using JEDEC-standard 3.3V I/O logic levels. It is composed of three input connections and one output connection required by the test logic defined by the standard.

Performing a TAP Reset

A reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This reset does not affect the operation of the devices, and may be performed while the device is operating. An MRST must be performed on the devices after power up.

Performing a Pause/Restart

When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan chain outputs the next bit in the chain twice. For example, if the value expected from the chain is 1010101, the device outputs a 11010101. This extra bit causes some testers to report an erroneous failure for the devices in a scan test. Therefore the tester should be configured to never enter the PAUSE-DR state.

Boundary Scan Hierarchy for 9-Mbit Device

Internally, the CY7C0833AV have two DIEs. Each DIE contain all the circuitry required to support boundary scan testing. The circuitry includes the TAP, TAP controller, instruction register, and data registers. The circuity and operation of the DIE boundary scan are described in detail below. The scan chain of each DIE are connected serially to form the scan chain of the CY7C0833AV as shown in Figure 5 on page 11. TMS and TCK are connected in parallel to each DIE to drive all TAP controllers in unison. In many cases, each DIE is supplied with the same instruction. In other cases, it might be useful to supply different instructions to each DIE. One example would be testing the device ID of one DIE while bypassing the others.

Each pin of FLEx18 family is typically connected to multiple DIEs. For connectivity testing with the EXTEST instruction, it is desirable to check the internal connections between DIEs and the external connections to the package. This is accomplished by merging the netlist of the devices with the netlist of the user’s circuit board. To facilitate boundary scan testing of the devices, Cypress provides the BSDL file for each DIE, the internal netlist of the device, and a description of the device scan chain. The user can use these materials to easily integrate the devices into the board’s boundary scan environment. Further information is found in the Cypress application note Using JTAG Boundary Scan For System in a Package (SIP) Dual-Port SRAMs.

Notes

20.The “X” in this diagram represents the counter upper bits

21.Boundary scan is IEEE 1149.1-compatible. See Performing a Pause/Restart on page 10 for deviation from strict 1149.1 compliance

Document #: 38-06059 Rev. *S Page 10 of 28

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