Cypress CY7C1370DV25 manual Ieee 1149.1 Serial Boundary Scan Jtag, TAP Controller State Diagram

CY7C1370DV25

CY7C1372DV25

Function (CY7C1372DV25)	WE	BWb	BWa
Read	H	x	x
Write – No Bytes Written	L	H	H
Write Byte a – (DQa and DQPa)	L	H	L
Write Byte b – (DQb and DQPb)	L	L	H
Write Both Bytes	L	L	L

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1370DV25/CY7C1372DV25 incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.

The CY7C1370DV25/CY7C1372DV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are inter- nally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.

TAP Controller State Diagram

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant

1 TEST-LOGIC RESET

0

0 RUN-TEST/

IDLE

1	SELECT	1	SELECT	1
	DR-SCAN		IR-SCAN

bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller Block Diagram

0		0
1		1
CAPTURE-DR		CAPTURE-IR
0		0
SHIFT-DR	0	SHIFT-IR	0
1		1
EXIT1-DR	1	EXIT1-IR	1
0		0
PAUSE-DR	0	PAUSE-IR	0
1		1
0		0
EXIT2-DR		EXIT2-IR
1		1

TDI

Selection Circuitry

									0
			Bypass Register
							2	1	0
	Instruction Register
	31	30	29	.	.	.	2	1	0
Identification Register
	x	.	.	.	.	.	2	1	0

Boundary Scan Register

Selection Circuitry

TDO

UPDATE-DR			UPDATE-IR
1	0	1
				0

TCK

TMS TAP CONTROLLER

The 0/1 next to each state represents the value of TMS at the rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating.

At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.

Document #: 38-05558 Rev. *D Page 10 of 27

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