CY7C1370DV25
CY7C1372DV25
Document #: 38-05558 Rev. *D Page 15 of 27
Identification Codes
Instruction Code Description
EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
119-Ball BGA Boundary Scan Order[12, 13]
Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID
1H4 23 F6 45 G4 67 L1
2T4 24E7 46A4 68M2
3T5 25D7 47G3 69N1
4T6 26H7 48C3 70P1
5R5 27G6 49B2 71K1
6L5 28E6 50B3 72L2
7R6 29D6 51A3 73N2
8U6 30C7 52C2 74P2
9R7 31B7 53A2 75R3
10 T7 32 C6 54 B1 76 T1
11 P6 33 A6 55 C1 77 R1
12 N7 34 C5 56 D2 78 T2
13 M6 35 B5 57 E1 79 L3
14 L7 36 G5 58 F2 80 R2
15 K6 37 B6 59 G1 81 T3
16 P7 38 D4 60 H2 82 L4
17 N6 39 B4 61 D1 83 N4
18 L6 40 F4 62 E2 84 P4
19 K7 41 M4 63 G2 85 Internal
20 J5 42 A5 64 H1
21 H6 43 K4 65 J3
22 G7 44 E4 66 2K
Notes:
12.Balls which are NC (No Connect) are pre-set LOW.
13.Bit# 85 is pre-set HIGH.
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