Cypress CY7C1370DV25, CY7C1372DV25

CY7C1370DV25

CY7C1372DV25

Document #: 38-05558 Rev. *D Page 25 of 27

Package Diagrams (continued)

51-85115-*B

119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)

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Contents

Main 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL Architecture CY7C1370DV25 CY7C1372DV25 Features Functional Description Logic Block Diagram-CY7C1370DV25 (512K x 36) CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev. *D Page 2 of 27 A0, A1, A C ZZ C CY7C1370DV25 CY7C1372DV25 Document #: 38-05558 Rev. *D Page 3 of 27 Pin Configurations (512K 36) (1M 18) MODE Pin Configurations 2345671 A B C D E F G H J K L M N P R T U CY7C1370DV25 (512K 36) 119-Ball BGA Pinout 2345671 A B C D E F G H J K L M N P R T U CY7C1370DV25 CY7C1372DV25 Pin Configurations CY7C1370DV25 (512K 36) CY7C1372DV25 (1M 18) 2345671 A B C D E F G H J K L M N P R Pin Definitions CY7C1370DV25 CY7C1372DV25 Introduction Pin Definitions Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Partial Write Cycle Description IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Controller State Diagram TAP Controller Block Diagram Page TAP Ti min g CY7C1370DV25 CY7C1372DV25 TAP AC Switching Characteristics 2.5V TAP AC Test Conditions 2.5V TAP AC Output Load Equivalent F DO T Identification Codes 119-Ball BGA Boundary Scan Order 165-Ball FBGA Boundary Scan Order Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Read/Write/Timing OE n-Out (DQ) I Switching Waveforms CLK ZZ LL INPUTS (except ZZ) DONT CARE Page Ordering Information Package Diagrams A 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050) Page Package Diagrams 51-85180-*A SOLDERPAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40MAX. 51-85180-*A Document History Page