Cypress CY7C1370DV25, CY7C1372DV25 Maximum Ratings , Operating Range , Electrical Characteristics

CY7C1370DV25
CY7C1372DV25
Document #: 38-05558 Rev. *D Page 17 of 27
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VDD Relative to GND........–0.5V to +3.6V
Supply Voltage on VDDQ Relative to GND......–0.5V to +VDD
DC to Outputs in Tri-State...................–0.5V to VDDQ + 0.5V
DC Input Voltage...................................–0.5V to VDD + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range Ambient Temperature VDD/VDDQ
Commercial 0°C to +70°C 2.5V ±5%
Industrial –40°C to +85°C
Electrical Characteristics Over the Operating Range[15, 16]
Parameter Description Test Conditions Min. Max. Unit
VDD Power Supply Voltage 2.375 2.625 V
VDDQ I/O Supply Voltage for 2.5V I/O 2.375 VDD V
VOH Output HIGH Voltage for 2.5V I/O, IOH = −1.0 mA 2.0 V
VOL Output LOW Voltage for 2.5V I/O, IOL= 1.0 mA 0.4 V
VIH Input HIGH Voltage[17] for 2.5V I/O 1.7 VDD + 0.3V V
VIL Input LOW Voltage[17] for 2.5V I/O –0.3 0.7 V
IXInput Leakage Current
except ZZ and MODE GND ≤ VI ≤ VDDQ –5 5µA
Input Current of MODE Input = VSS –30 µA
Input = VDD 5µA
Input Current of ZZ Input = VSS –5 µA
Input = VDD 30 µA
IOZ Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled –5 5µA
IDD VDD Operating Supply VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz 350 mA
5.0-ns cycle, 200 MHz 300 mA
6.0-ns cycle, 167 MHz 275 mA
ISB1 Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = fMAX =
1/tCYC
4.0-ns cycle, 250 MHz 160 mA
5.0-ns cycle, 200 MHz 150 mA
6.0-ns cycle, 167 MHz 140 mA
ISB2 Automatic CE
Power-down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
f = 0
All speed grades 70 mA
ISB3 Automatic CE
Power-down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz 135 mA
5.0-ns cycle, 200 MHz 130 mA
6.0-ns cycle, 167 MHz 125 mA
ISB4 Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0 All speed grades 80 mA
Notes:
15.Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).
16.TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
17.Tested initially and after any design or process change that may affect these parameters.
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