CY7C1370DV25

CY7C1372DV25

Document History Page

Document Title: CY7C1370DV25/CY7C1372DV25 18-Mbit (512K x 36/1M x 18)

Pipelined SRAM with NoBL™ Architecture

Document Number: 38-05558

REV.

ECN No.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

**

254509

See ECN

RKF

New data sheet

 

 

 

 

 

*A

288531

See ECN

SYT

Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for

 

 

 

 

non-compliance with 1149.1

 

 

 

 

Removed 225 Mhz Speed Bin

 

 

 

 

Added lead-free information for 100-Pin TQFP, 119 BGA and 165 FBGA

 

 

 

 

package

 

 

 

 

Added comment of ‘Lead-free BG packages availability’ below the Ordering

 

 

 

 

Information

*B

326078

See ECN

PCI

Address expansion pins/balls in the pinouts for all packages are modified as

 

 

 

 

per JEDEC standard

 

 

 

 

Added description on EXTEST Output Bus Tri-State

 

 

 

 

Changed description on the Tap Instruction Set Overview and Extest

 

 

 

 

Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to 28.66 and

 

 

 

 

4.08 °C/W respectively

 

 

 

 

Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to 23.8 and 6.2

 

 

 

 

°C/W respectively

 

 

 

 

Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to 20.7 and

 

 

 

 

4.0 °C/W respectively

 

 

 

 

Modified VOL, VOH test conditions

 

 

 

 

Removed comment of ‘Lead-free BG packages availability’ below the

 

 

 

 

Ordering Information

 

 

 

 

Updated Ordering Information Table

*C

418125

See ECN

NXR

Converted from Preliminary to Final

 

 

 

 

Changed address of Cypress Semiconductor Corporation on Page# 1 from

 

 

 

 

“3901 North First Street” to “198 Champion Court”

 

 

 

 

Changed the description of IX from Input Load Current to Input Leakage

 

 

 

 

Current on page# 18

 

 

 

 

Changed the IX current values of MODE on page # 18 from –5 A and 30 A

 

 

 

 

to –30 A and 5 A

 

 

 

 

Changed the IX current values of ZZ on page # 18 from –30 A and 5 A

 

 

 

 

to –5 A and 30 A

 

 

 

 

Changed VIH < VDD to VIH < VDDon page # 18

 

 

 

 

Updated Ordering Information Table

*D

475677

See ECN

VKN

Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.

 

 

 

 

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP

 

 

 

 

AC Switching Characteristics table.

 

 

 

 

Updated the Ordering Information table.

Document #: 38-05558 Rev. *D

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Cypress CY7C1372DV25, CY7C1370DV25 manual Document History, ECN No Issue Date Orig. Description of Change