Cypress CY7C1370DV25 manual Logic Block Diagram-CY7C1372DV25 1M x, Selection Guide

CY7C1370DV25

CY7C1372DV25

Logic Block Diagram-CY7C1372DV25 (1M x 18)

A0, A1, A

ADDRESS

REGISTER 0

A1

D1

Q1 A1'

MODE

A0

D0 BURST Q0 A0'

ADV/LD

LOGIC

CLK

C

C

CEN

WRITE ADDRESS

WRITE ADDRESS

REGISTER 1

REGISTER 2

O

O

U

U

T

T

ADV/LD

S

P

D

P

E

U

A

U

WRITE REGISTRY

N

T

T

T

MEMORY

S

R

A

B

BWa

AND DATA COHERENCY

WRITE

E

DQs

ARRAY

E

S

U

CONTROL LOGIC

DRIVERS

A

G

DQPa

T

F

BWb

M

I

E

F

DQPb

P

S

E

E

T

S

R

R

E

I

S

WE

R

N

S

G

E

E

INPUT

E

INPUT

E

REGISTER 1

REGISTER 0

OE

READ LOGIC

CE1

CE2

CE3

ZZ

Sleep

Control

Selection Guide

	250 MHz	200 MHz	167 MHz	Unit
Maximum Access Time	2.6	3.0	3.4	ns
Maximum Operating Current	350	300	275	mA
Maximum CMOS Standby Current	70	70	70	mA

Document #: 38-05558 Rev. *D Page 2 of 27

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