CY7C1370DV25

CY7C1372DV25

Switching Waveforms (continued)

NOP,STALL and DESELECT Cycles[24, 25, 27]

1

2

3

4

5

6

7

8

9

10

CLK

CEN

CE

ADV/LD

WE

BWx

ADDRESS A1 A2 A3 A4 A5

tCHZ

Data

In-Out (DQ)

WRITE

D(A1)

READ Q(A2)

STALL

D(A1)

READ

Q(A3)

Q(A2)

Q(A3)

 

D(A4)

Q(A5)

WRITE

STALL

NOP

READ

DESELECT CONTINUE

D(A4)

 

 

Q(A5)

DESELECT

DON’T CARE

UNDEFINED

 

 

ZZ Mode Timing[28, 29]

CLK

ZZ

ISUPPLY

ALL INPUTS (except ZZ)

Outputs (Q)

tZZ

t ZZI

I DDZZ

High-Z

DON’T CARE

t ZZREC

t RZZI

DESELECT or READ Only

Notes:

27.The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle

28.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.

29.I/Os are in High-Z when exiting ZZ sleep mode.

Document #: 38-05558 Rev. *D

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Cypress CY7C1372DV25, CY7C1370DV25 manual NOP,STALL and Deselect Cycles24, 25, ZZ Mode Timing28