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Cypress CY7C1474V25, CY7C1470V25 manual 2.5V TAP AC Test Conditions, 1.8V TAP AC Test Conditions

Models: CY7C1474V25 CY7C1470V25 CY7C1472V25

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2.5V TAP AC Test Conditions

CY7C1470V25

CY7C1472V25

CY7C1474V25

2.5V TAP AC Test Conditions

Input pulse levels	VSS to 2.5V
Input rise and fall time	1 ns
Input timing reference levels	1.25V
Output reference levels	1.25V
Test load termination supply voltage	1.25V

1.8V TAP AC Test Conditions

Input pulse levels	0.2V to VDDQ – 0.2
Input rise and fall time	1 ns
Input timing reference levels	0.9V
Output reference levels	0.9V
Test load termination supply voltage	0.9V

2.5V TAP AC Output Load Equivalent

1.8V TAP AC Output Load Equivalent

1.25V

0.9V

50Ω

50Ω

TDO

TDO

ZO= 50Ω

20pF

ZO= 50Ω

20pF

TAP DC Electrical Characteristics And Operating Conditions

(0°C < T < +70°C; V

DD

= 2.5V ±0.125V unless otherwise noted)[11]

A

Parameter

Description

Test Conditions

Min.

Max.

Unit

VOH1

Output HIGH Voltage

IOH = –1.0 mA

VDDQ = 2.5V

1.7

V

VOH2

Output HIGH Voltage

IOH = –100 ∝A

VDDQ = 2.5V

2.1

V

VDDQ = 1.8V

1.6

V

VOL1

Output LOW Voltage

IOL = 1.0 mA

VDDQ = 2.5V

0.4

V

VOL2

Output LOW Voltage

IOL = 100 ∝A

VDDQ = 2.5V

0.2

V

VDDQ = 1.8V

0.2

V

VIH

Input HIGH Voltage

VDDQ = 2.5V

1.7

VDD + 0.3

V

VDDQ = 1.8V

1.26

VDD + 0.3

V

VIL

Input LOW Voltage

VDDQ = 2.5V

–0.3

0.7

V

VDDQ = 1.8V

–0.3

0.36

V

IX

Input Load Current

GND ≤ VI ≤ VDDQ

–5

5

∝A

Identification Register Definitions

Instruction Field

CY7C1470V25

CY7C1472V25

CY7C1474V25

Description

(2M x 36)

(4M x 18)

(1M x 72)

Revision Number (31:29)

000

000

000

Describes the version number

Device Depth (28:24)

01011

01011

01011

Reserved for internal use

Architecture/Memory Type(23:18)

001000

001000

001000

Defines memory type and archi-

tecture

Bus Width/Density(17:12)

100100

010100

110100

Defines width and density

Cypress JEDEC ID Code (11:1)

00000110100

00000110100

00000110100

Allows unique identification of

SRAM vendor

ID Register Presence Indicator (0)

1

1

1

Indicates the presence of an ID

register

Note:

11. All voltages referenced to VSS (GND).

Document #: 38-05290 Rev. *I

Page 13 of 28

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Cypress CY7C1474V25 manual 2.5V TAP AC Test Conditions, 1.8V TAP AC Test Conditions, 2.5V TAP AC Output Load Equivalent

Contents

Logic Block Diagram-CY7C1470V25 2M x FeaturesCY7C1470V25 CY7C1472V25 CY7C1474V25 Functional DescriptionLogic Block Diagram-CY7C1474V25 1M x Logic Block Diagram-CY7C1472V25 4M xSelection Guide CY7C1470V25 CY7C1472V25 CY7C1474V25CY7C1470V25 CY7C1472V25 CY7C1474V25 Pin Configurations 100-pin TQFP PinoutCY7C1470V25 2M ×165-ball FBGA 15 x 17 x 1.4 mm Pinout CY7C1470V25 2M x Pin Configurations continuedCY7C1472V25 4M x CY7C1470V25 CY7C1472V25 CY7C1474V25CY7C1474V25 1M x Pin Configurations continued 209-ball FBGA 14 x 22 x 1.76 mm PinoutPin Definitions CY7C1470V25 CY7C1472V25 CY7C1474V25CY7C1472V25 CY7C1470V25CY7C1474V25 Pin Definitions continuedBurst Read Accesses Single Read AccessesSingle Write Accesses Burst Write AccessesLinear Burst Address Table MODE = GND ZZ Mode Electrical CharacteristicsInterleaved Burst Address Table MODE = Floating or VDD CY7C1470V25 CY7C1472V25 CY7C1474V25CY7C1470V25 CY7C1472V25 CY7C1474V25 Partial Write Cycle Description1, 2, 3TAP Controller State Diagram TAP Controller Block DiagramIEEE 1149.1 Serial Boundary Scan JTAG Test MODE SELECT TMSBypass Register Instruction RegisterBoundary Scan Register Identification ID RegisterTAP Timing TAP AC Switching Characteristics Over the Operating Range9BYPASS Reserved2.5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions1.8V TAP AC Test Conditions 2.5V TAP AC Output Load EquivalentIdentification Codes Scan Register SizesCY7C1470V25 CY7C1472V25Boundary Scan Exit Order 4M x Boundary Scan Exit Order 2MCY7C1470V25 CY7C1472V25 CY7C1474V25 CY7C1470V25 CY7C1472V25 CY7C1474V25 Boundary Scan Exit Order 1M xMaximum Ratings Electrical Characteristics Over the Operating Range12Operating Range CY7C1470V25 CY7C1472V25 CY7C1474V25Thermal Resistance14 Capacitance14AC Test Loads and Waveforms CY7C1470V25 CY7C1472V25 CY7C1474V25CY7C1470V25 CY7C1472V25 CY7C1474V25 Switching Characteristics Over the Operating Range 15CY7C1470V25 CY7C1472V25 CY7C1474V25 Switching WaveformsRead/Write/Timing21, 22 CY7C1470V25 CY7C1472V25 CY7C1474V25 Switching Waveforms continuedNOP, STALL and DESELECT Cycles21 ZZ Mode Timing25CY7C1470V25 CY7C1472V25 CY7C1474V25 Ordering InformationCY7C1470V25 CY7C1472V25 CY7C1474V25 Ordering Information continuedCY7C1470V25 CY7C1472V25 CY7C1474V25 Package Diagrams100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm + FeedbackCY7C1470V25 CY7C1472V25 CY7C1474V25 Package Diagrams165-Ball FBGA 15 x 17 x 1.4 mm Page 25 ofCY7C1470V25 CY7C1472V25 CY7C1474V25 Package Diagrams continued209-Ball FBGA 14 x 22 x 1.76 mm + FeedbackIssue Date Document History PageCY7C1470V25 CY7C1472V25 CY7C1474V25 Document NumberPage 28 of CY7C1470V25 CY7C1472V25 CY7C1474V25