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Cypress manual CY7C1470V25 CY7C1472V25 CY7C1474V25, Page 28 of

Models: CY7C1474V25 CY7C1470V25 CY7C1472V25

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CY7C1470V25

CY7C1472V25

CY7C1474V25

Document Title: CY7C1470V25/CY7C1472V25/CY7C1474V25 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture

Document Number: 38-05290

472335

See ECN

VKN

Corrected the typo in the pin configuration for 209-Ball FBGA pinout (Corrected the ball name for H9 to VSS from VSSQ).

Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table.

Updated the Ordering Information table.

Document #: 38-05290 Rev. *I

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Contents

Features Logic Block Diagram-CY7C1470V25 2M xCY7C1470V25 CY7C1472V25 CY7C1474V25 Functional DescriptionLogic Block Diagram-CY7C1472V25 4M x Logic Block Diagram-CY7C1474V25 1M xSelection Guide CY7C1470V25 CY7C1472V25 CY7C1474V25Pin Configurations 100-pin TQFP Pinout CY7C1470V25 CY7C1472V25 CY7C1474V25CY7C1470V25 2M ×Pin Configurations continued 165-ball FBGA 15 x 17 x 1.4 mm Pinout CY7C1470V25 2M xCY7C1472V25 4M x CY7C1470V25 CY7C1472V25 CY7C1474V25Pin Configurations continued 209-ball FBGA 14 x 22 x 1.76 mm Pinout CY7C1474V25 1M xPin Definitions CY7C1470V25 CY7C1472V25 CY7C1474V25CY7C1470V25 CY7C1472V25CY7C1474V25 Pin Definitions continuedSingle Read Accesses Burst Read AccessesSingle Write Accesses Burst Write AccessesZZ Mode Electrical Characteristics Linear Burst Address Table MODE = GNDInterleaved Burst Address Table MODE = Floating or VDD CY7C1470V25 CY7C1472V25 CY7C1474V25Partial Write Cycle Description1, 2, 3 CY7C1470V25 CY7C1472V25 CY7C1474V25TAP Controller Block Diagram TAP Controller State DiagramIEEE 1149.1 Serial Boundary Scan JTAG Test MODE SELECT TMSInstruction Register Bypass RegisterBoundary Scan Register Identification ID RegisterTAP AC Switching Characteristics Over the Operating Range9 TAP TimingBYPASS ReservedTAP DC Electrical Characteristics And Operating Conditions 2.5V TAP AC Test Conditions1.8V TAP AC Test Conditions 2.5V TAP AC Output Load EquivalentScan Register Sizes Identification CodesCY7C1470V25 CY7C1472V25Boundary Scan Exit Order 4M x Boundary Scan Exit Order 2MCY7C1470V25 CY7C1472V25 CY7C1474V25 Boundary Scan Exit Order 1M x CY7C1470V25 CY7C1472V25 CY7C1474V25Electrical Characteristics Over the Operating Range12 Maximum RatingsOperating Range TemperatureCapacitance14 Thermal Resistance14AC Test Loads and Waveforms CY7C1470V25 CY7C1472V25 CY7C1474V25Switching Characteristics Over the Operating Range 15 CY7C1470V25 CY7C1472V25 CY7C1474V25CY7C1470V25 CY7C1472V25 CY7C1474V25 Switching WaveformsRead/Write/Timing21, 22 Switching Waveforms continued CY7C1470V25 CY7C1472V25 CY7C1474V25NOP, STALL and DESELECT Cycles21, 22 ZZ Mode Timing25Ordering Information CY7C1470V25 CY7C1472V25 CY7C1474V25Ordering Information continued CY7C1470V25 CY7C1472V25 CY7C1474V25Package Diagrams CY7C1470V25 CY7C1472V25 CY7C1474V25100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm + FeedbackPackage Diagrams CY7C1470V25 CY7C1472V25 CY7C1474V25165-Ball FBGA 15 x 17 x 1.4 mm Page 25 ofPackage Diagrams continued CY7C1470V25 CY7C1472V25 CY7C1474V25209-Ball FBGA 14 x 22 x 1.76 mm + FeedbackDocument History Page Issue DateCY7C1470V25 CY7C1472V25 CY7C1474V25 Document NumberCY7C1470V25 CY7C1472V25 CY7C1474V25 Page 28 of