CY7C1470V25
CY7C1472V25
CY7C1474V25
Pin Configurations (continued)
CY7C1474V25 (1M x 72)
| 1 | 2 | 3 |
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A | DQg | DQg |
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| CE2 | A |
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| A | DQb | DQb | |||||||||||
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B | DQg | DQg |
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| g | NC |
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| f | DQb | DQb | |||||
BWS | BWS | WE |
| BWS | BWS | |||||||||||||||||||||||||||||
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C | DQg | DQg |
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| d | NC/576M |
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| 1 |
| NC |
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| a | DQb | DQb | ||||||||
BWS | BWS | CE |
| BWS | BWS | |||||||||||||||||||||||||||||
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D | DQg | DQg |
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| VSS |
| NC | NC/1G |
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| NC |
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| VSS | DQb | DQb | ||||||||
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E | DQPg | DQPc |
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| VDDQ |
| VDDQ | VDD |
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| VDD | VDD |
| VDDQ |
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| VDDQ | DQPf | DQPb | |||||||||||||||
F | DQc | DQc |
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| VSS |
| VSS | VSS |
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| NC | VSS |
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| VSS |
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| VSS | DQf | DQf | |||||||||||||
G | DQc | DQc |
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| VDDQ |
| VDDQ | VDD |
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| NC | VDD |
| VDDQ |
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| VDDQ | DQf | DQf | ||||||||||||||
H | DQc | DQc |
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| VSS |
| VSS | VSS |
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| NC | VSS |
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| VSS |
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| VSS | DQf | DQf | |||||||||||||
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J | DQc | DQc |
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| VDDQ |
| VDDQ | VDD |
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| NC | VDD |
| VDDQ |
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| VDDQ | DQf | DQf | ||||||||||||||
K | NC | NC |
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| CLK |
| NC | VSS |
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| VSS |
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| CEN |
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| NC |
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| NC | NC | NC | ||||||||||||||||||||||
L | DQh | DQh |
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| VDDQ |
| VDDQ | VDD |
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| NC | VDD |
| VDDQ |
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| VDDQ | DQa | DQa | ||||||||||||||
M | DQh | DQh |
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| VSS |
| VSS | VSS |
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| NC | VSS |
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| VSS |
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| VSS | DQa | DQa | |||||||||||||
N | DQh | DQh |
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| VDDQ |
| VDDQ | VDD |
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| NC | VDD |
| VDDQ |
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| VDDQ | DQa | DQa | ||||||||||||||
P | DQh | DQh |
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| VSS |
| VSS | VSS |
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| ZZ | VSS |
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| VSS |
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| VSS | DQa | DQa | |||||||||||||
R | DQPd | DQPh |
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| VDDQ |
| VDDQ | VDD |
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| VDD | VDD |
| VDDQ |
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| VDDQ | DQPa | DQPe | |||||||||||||||
T | DQd | DQd |
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| VSS |
| NC | NC | MODE | NC |
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| VSS | DQe | DQe | ||||||||||||||||
U | DQd | DQd | NC/144M |
| A | A |
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| A | A |
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| A | NC/288M | DQe | DQe | |||||||||||||||||
V | DQd | DQd |
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| A |
| A | A |
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| A1 | A |
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| A | DQe | DQe | |||||||||||||
W | DQd | DQd |
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| TMS |
| TDI | A |
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| A0 | A |
| TDO |
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| TCK | DQe | DQe | ||||||||||||||
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Pin Definitions
| Pin Name | I/O Type | Pin Description | ||||||
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| A0 | Input- | Address Inputs used to select one of the address locations. Sampled at the rising edge of | ||||||
| A1 | Synchronous | the CLK. | ||||||
| A |
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| a | Input- | Byte Write Select Inputs, active LOW. Qualified with |
| to conduct writes to the SRAM. | |||
| BW | WE | |||||||
| BWb | Synchronous | Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, | ||||||
| BWc |
| BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf | ||||||
| BWd |
| controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh. | ||||||
| BWe |
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| BWf |
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| BWg |
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| BWh |
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| Input- | Write Enable Input, active LOW. Sampled on the rising edge of CLK if |
| is active LOW. This | ||
| WE | CEN | |||||||
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| Synchronous | signal must be asserted LOW to initiate a write sequence. | ||||
Document #: | Page 5 of 28 |
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