Cypress CY7C1470V25 manual Clock input to the Jtag circuitry, Power supply for the I/O circuitry

					CY7C1470V25
					CY7C1472V25
					CY7C1474V25
	Pin Definitions (continued)
		Pin Name		I/O Type	Pin Description
				Input-	Advance/Load Input used to advance the on-chip address counter or load a new address.
		ADV/LD
				Synchronous	When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
					new address can be loaded into the device for an access. After being deselected, ADV/LD should
					be driven LOW in order to load a new address.
		CLK		Input-	Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with
						CEN.
				Clock	CLK is only recognized if CEN is active LOW.
			1	Input-	Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
		CE
				Synchronous	CE2 and CE3 to select/deselect the device.
		CE2		Input-	Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
				Synchronous	CE1 and CE3 to select/deselect the device.
			3	Input-	Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
		CE
				Synchronous	CE1 and CE2 to select/deselect the device.
				Input-	Output Enable, active LOW. Combined with the synchronous logic block inside the device to
		OE
				Asynchronous	control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
					When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
					the data portion of a write sequence, during the first clock when emerging from a deselected state
					and when the device has been deselected.
				Input-	Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
		CEN
				Synchronous	SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
					deselect the device, CEN can be used to extend the previous cycle when required.
		DQs		I/O-	Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
				Synchronous	by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
					specified by A[18:0] during the previous clock rise of the read cycle. The direction of the pins is
					controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
					as outputs. When HIGH, DQa–DQhare placed in a tri-state condition. The outputs are automat-
					ically tri-stated during the data portion of a write sequence, during the first clock when emerging
					from a deselected state, and when the device is deselected, regardless of the state of OE.
		DQPX		I/O-	Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[71:0]. During
				Synchronous	write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by
					BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf,
					DQPg is controlled by BWg, DQPh is controlled by BWh.
		MODE		Input Strap Pin	Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
					Pulled LOW selects the linear burst order. MODE should not change states during operation.
					When left floating MODE will default HIGH, to an interleaved burst order.
		TDO		JTAG Serial	Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
				Output
				Synchronous
		TDI		JTAG Serial Input	Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
				Synchronous
		TMS		Test Mode Select	This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
				Synchronous
		TCK		JTAG Clock	Clock input to the JTAG circuitry.
		VDD		Power Supply	Power supply inputs to the core of the device.
		VDDQ		I/O Power Supply	Power supply for the I/O circuitry.
		VSS		Ground	Ground for the device. Should be connected to ground of the system.
		NC		–	No connects. This pin is not connected to the die.
		NC(144M,		–	These pins are not connected. They will be used for expansion to the 144M, 288M, 576M and
		288M,			1G densities.
		576M, 1G)
		ZZ		Input-	ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
				Asynchronous	with data integrity preserved. For normal operation, this pin has to be LOW or left floating.
					ZZ pin has an internal pull-down.
Document #: 38-05290 Rev. *I					Page 6 of 28

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