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| CY7C1470V25 | |||
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| CY7C1472V25 | |||
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| CY7C1474V25 | |||
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| Pin Definitions (continued) | |||||||||||||
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| Pin Name | I/O Type | Pin Description | ||||||||||
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| Input- | Advance/Load Input used to advance the | |||||
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| ADV/LD |
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| Synchronous | When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a | |||||
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| new address can be loaded into the device for an access. After being deselected, ADV/LD should | |||
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| be driven LOW in order to load a new address. | |||
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| CLK | Input- | Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with |
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CEN. | ||||||||||||||
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| Clock | CLK is only recognized if CEN is active LOW. | |||||
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| 1 |
| Input- | Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with | ||||||||
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| CE | ||||||||||||
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| Synchronous | CE2 and CE3 to select/deselect the device. | |||||
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| CE2 | Input- | Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with | ||||||||||
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| Synchronous | CE1 and CE3 to select/deselect the device. | |||||
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| 3 |
| Input- | Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with | ||||||||
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| CE | ||||||||||||
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| Synchronous | CE1 and CE2 to select/deselect the device. | |||||
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| Input- | Output Enable, active LOW. Combined with the synchronous logic block inside the device to | |||||||
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| OE | ||||||||||||
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| Asynchronous | control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. | |||||
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| When deasserted HIGH, I/O pins are | |||
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| the data portion of a write sequence, during the first clock when emerging from a deselected state | |||
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| and when the device has been deselected. | |||
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| Input- | Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the | |||||||
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| CEN | ||||||||||||
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| Synchronous | SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not | |||||
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| deselect the device, CEN can be used to extend the previous cycle when required. | |||
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| DQs | I/O- | Bidirectional Data I/O lines. As inputs, they feed into an | ||||||||||
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| Synchronous | by the rising edge of CLK. As outputs, they deliver the data contained in the memory location | |||||
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| specified by A[18:0] during the previous clock rise of the read cycle. The direction of the pins is | |||
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| controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave | |||
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| as outputs. When HIGH, | |||
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| ically | |||
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| from a deselected state, and when the device is deselected, regardless of the state of OE. | |||
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| DQPX | I/O- | Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[71:0]. During | ||||||||||
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| Synchronous | write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by | |||||
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| BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, | |||
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| DQPg is controlled by BWg, DQPh is controlled by BWh. | |||
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| MODE | Input Strap Pin | Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. | ||||||||||
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| Pulled LOW selects the linear burst order. MODE should not change states during operation. | |||
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| When left floating MODE will default HIGH, to an interleaved burst order. | |||
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| TDO | JTAG Serial | Serial | ||||||||||
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| Output |
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| Synchronous |
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| TDI | JTAG Serial Input | Serial | ||||||||||
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| Synchronous |
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| TMS | Test Mode Select | This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. | ||||||||||
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| Synchronous |
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| TCK | JTAG Clock | Clock input to the JTAG circuitry. | ||||||||||
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| VDD | Power Supply | Power supply inputs to the core of the device. | ||||||||||
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| VDDQ | I/O Power Supply | Power supply for the I/O circuitry. | ||||||||||
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| VSS | Ground | Ground for the device. Should be connected to ground of the system. | ||||||||||
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| NC | – | No connects. This pin is not connected to the die. | ||||||||||
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| NC(144M, | – | These pins are not connected. They will be used for expansion to the 144M, 288M, 576M and | ||||||||||
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| 288M, |
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| 1G densities. | ||||||||
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| 576M, 1G) |
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| ZZ | Input- | ZZ “Sleep” Input. This active HIGH input places the device in a | ||||||||||
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| Asynchronous | with data integrity preserved. For normal operation, this pin has to be LOW or left floating. | |||||
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| ZZ pin has an internal | |||
Document #: | Page 6 of 28 |
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