Cypress Logic Block Diagram-CY7C1472V25 4M x, Logic Block Diagram-CY7C1474V25 1M x, + Feedback

CY7C1470V25

CY7C1472V25

CY7C1474V25

Logic Block Diagram-CY7C1472V25 (4M x 18)
	A0, A1, A	ADDRESS
		REGISTER 0		A1	D1	Q1 A1'
	MODE			A0	D0 BURST Q0 A0'
				ADV/LD		LOGIC
CLK	C
				C
CEN
		WRITE ADDRESS		WRITE ADDRESS
		REGISTER 1		REGISTER 2
									O		O
									U		U
								S	T	D	T
									P		P
	ADV/LD							E	U	A	U
				WRITE REGISTRY				N	T	T	T
							MEMORY	S	R	A	B
	BWa			AND DATA COHERENCY		WRITE		E
							ARRAY		E	S	U
				CONTROL LOGIC		DRIVERS		A	G
										T	F
	BWb							M	I	E	F
								P	S	E	E
								S	T	R	R
									E	I	S
	WE								R	N
									S
										G
									E		E
							INPUT	E		INPUT	E
							REGISTER 1			REGISTER 0
	OE		READ LOGIC
	CE1
	CE2
	CE3
	ZZ		Sleep
			Control

DQs DQPa DQPb

Logic Block Diagram-CY7C1474V25 (1M x 72)

	A0, A1, A	ADDRESS
		REGISTER 0		A1	D1	Q1 A1'
	MODE			A0	D0 BURST Q0 A0'
				ADV/LD		LOGIC
CLK	C
				C
CEN
		WRITE ADDRESS		WRITE ADDRESS
		REGISTER 1		REGISTER 2
									O		O
									U		U
									T		T
	ADV/LD							S	P	D	P
								E	U	A	U
	BWa			WRITE REGISTRY				N	T	T	T
							MEMORY	S	R	A
	BWb			AND DATA COHERENCY		WRITE		E		S	B
				CONTROL LOGIC			ARRAY	A	E		U
	BWc					DRIVERS			G	T	F
	BWd							M	I	E	F
								P	S	E	E
	BWe							S	T	R	R
									E
	BWf									I	S
									R	N
	BWg								S	G
									E		E
	BWh
	WE
							INPUT	E		INPUT	E
							REGISTER 1			REGISTER 0
	OE		READ LOGIC
	CE1
	CE2
	CE3
	ZZ		Sleep
			Control

DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh

Selection Guide

	250 MHz	200 MHz	167 MHz	Unit
Maximum Access Time	3.0	3.0	3.4	ns
Maximum Operating Current	450	450	400	mA
Maximum CMOS Standby Current	120	120	120	mA

Document #: 38-05290 Rev. *I Page 2 of 28

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