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Cypress manual Boundary Scan Exit Order 1M x, CY7C1470V25 CY7C1472V25 CY7C1474V25

Models: CY7C1474V25 CY7C1470V25 CY7C1472V25

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Boundary Scan Exit Order (1M x 72)

CY7C1470V25

CY7C1472V25

CY7C1474V25

Boundary Scan Exit Order (1M x 72)

Bit #	209-Ball ID		Bit #	209-Ball ID		Bit #	209-Ball ID		Bit #	209-Ball ID
1	A1		29	T1		57	U10		85	B11

2	A2		30	T2		58	T11		86	B10

3	B1		31	U1		59	T10		87	A11

4	B2		32	U2		60	R11		88	A10

5	C1		33	V1		61	R10		89	A7

6	C2		34	V2		62	P11		90	A5

7	D1		35	W1		63	P10		91	A9

8	D2		36	W2		64	N11		92	U8

9	E1		37	T6		65	N10		93	A6

10	E2		38	V3		66	M11		94	D6

11	F1		39	V4		67	M10		95	K6

12	F2		40	U4		68	L11		96	B6

13	G1		41	W5		69	L10		97	K3

14	G2		42	V6		70	P6		98	A8

15	H1		43	W6		71	J11		99	B4

16	H2		44	V5		72	J10		100	B3

17	J1		45	U5		73	H11		101	C3

18	J2		46	U6		74	H10		102	C4

19	L1		47	W7		75	G11		103	C8

20	L2		48	V7		76	G10		104	C9

21	M1		49	U7		77	F11		105	B9

22	M2		50	V8		78	F10		106	B8

23	N1		51	V9		79	E10		107	A4

24	N2		52	W11		80	E11		108	C6

25	P1		53	W10		81	D11		109	B7

26	P2		54	V11		82	D10		110	A3

27	R2		55	V10		83	C11

28	R1		56	U11		84	C10

Document #: 38-05290 Rev. *I

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Cypress manual Boundary Scan Exit Order 1M x, CY7C1470V25 CY7C1472V25 CY7C1474V25

Contents

Features Logic Block Diagram-CY7C1470V25 2M xCY7C1470V25 CY7C1472V25 CY7C1474V25 Functional DescriptionLogic Block Diagram-CY7C1472V25 4M x Logic Block Diagram-CY7C1474V25 1M xSelection Guide CY7C1470V25 CY7C1472V25 CY7C1474V25Pin Configurations 100-pin TQFP Pinout CY7C1470V25 CY7C1472V25 CY7C1474V25CY7C1470V25 2M ×Pin Configurations continued 165-ball FBGA 15 x 17 x 1.4 mm Pinout CY7C1470V25 2M xCY7C1472V25 4M x CY7C1470V25 CY7C1472V25 CY7C1474V25Pin Configurations continued 209-ball FBGA 14 x 22 x 1.76 mm Pinout CY7C1474V25 1M xPin Definitions CY7C1470V25 CY7C1472V25 CY7C1474V25CY7C1470V25 CY7C1472V25CY7C1474V25 Pin Definitions continuedSingle Read Accesses Burst Read AccessesSingle Write Accesses Burst Write AccessesZZ Mode Electrical Characteristics Linear Burst Address Table MODE = GNDInterleaved Burst Address Table MODE = Floating or VDD CY7C1470V25 CY7C1472V25 CY7C1474V25Partial Write Cycle Description1, 2, 3 CY7C1470V25 CY7C1472V25 CY7C1474V25TAP Controller Block Diagram TAP Controller State DiagramIEEE 1149.1 Serial Boundary Scan JTAG Test MODE SELECT TMSInstruction Register Bypass RegisterBoundary Scan Register Identification ID RegisterTAP AC Switching Characteristics Over the Operating Range9 TAP TimingBYPASS ReservedTAP DC Electrical Characteristics And Operating Conditions 2.5V TAP AC Test Conditions1.8V TAP AC Test Conditions 2.5V TAP AC Output Load EquivalentScan Register Sizes Identification CodesCY7C1470V25 CY7C1472V25Boundary Scan Exit Order 4M x Boundary Scan Exit Order 2MCY7C1470V25 CY7C1472V25 CY7C1474V25 Boundary Scan Exit Order 1M x CY7C1470V25 CY7C1472V25 CY7C1474V25Electrical Characteristics Over the Operating Range12 Maximum RatingsOperating Range CY7C1470V25 CY7C1472V25 CY7C1474V25Capacitance14 Thermal Resistance14AC Test Loads and Waveforms CY7C1470V25 CY7C1472V25 CY7C1474V25Switching Characteristics Over the Operating Range 15 CY7C1470V25 CY7C1472V25 CY7C1474V25CY7C1470V25 CY7C1472V25 CY7C1474V25 Switching WaveformsRead/Write/Timing21, 22 Switching Waveforms continued CY7C1470V25 CY7C1472V25 CY7C1474V25NOP, STALL and DESELECT Cycles21 ZZ Mode Timing25Ordering Information CY7C1470V25 CY7C1472V25 CY7C1474V25Ordering Information continued CY7C1470V25 CY7C1472V25 CY7C1474V25Package Diagrams CY7C1470V25 CY7C1472V25 CY7C1474V25100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm + FeedbackPackage Diagrams CY7C1470V25 CY7C1472V25 CY7C1474V25165-Ball FBGA 15 x 17 x 1.4 mm Page 25 ofPackage Diagrams continued CY7C1470V25 CY7C1472V25 CY7C1474V25209-Ball FBGA 14 x 22 x 1.76 mm + FeedbackDocument History Page Issue DateCY7C1470V25 CY7C1472V25 CY7C1474V25 Document NumberCY7C1470V25 CY7C1472V25 CY7C1474V25 Page 28 of