Cypress CY7C1472V25 Linear Burst Address Table MODE = GND, ZZ Mode Electrical Characteristics

CY7C1470V25

CY7C1472V25

CY7C1474V25

CY7C1474V25, BWa,b,c,d for CY7C1470V25 and BWa,b for CY7C1472V25) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW.

Linear Burst Address Table (MODE = GND)

First	Second	Third	Fourth
Address	Address	Address	Address
A1,A0	A1,A0	A1,A0	A1,A0
00	01	10	11
01	10	11	00
10	11	00	01
11	00	01	10

Interleaved Burst Address Table (MODE = Floating or VDD)

First	Second	Third	Fourth
Address	Address	Address	Address
A1,A0	A1,A0	A1,A0	A1,A0
00	01	10	11
01	00	11	10
10	11	00	01
11	10	01	00

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min.

Max.

Unit

IDDZZ

Sleep mode standby current

ZZ > VDD − 0.2V

120

mA

tZZS

Device operation to ZZ

ZZ > VDD − 0.2V

2tCYC

ns

tZZREC

ZZ recovery time

ZZ < 0.2V

2tCYC

ns

tZZI

ZZ active to sleep current

This parameter is sampled

2tCYC

ns

tRZZI

ZZ Inactive to exit sleep current

This parameter is sampled

0

ns

Truth Table [1, 2, 3, 4, 5, 6, 7]

Address

Operation

Used

CE

ZZ

ADV/LD

WE

BWx

OE

CEN

CLK

DQ

Deselect Cycle

None

H

L

L

X

X

X

L

L-H

Tri-State

Continue Deselect Cycle

None

X

L

H

X

X

X

L

L-H

Tri-State

Read Cycle (Begin Burst)

External

L

L

L

H

X

L

L

L-H

Data Out (Q)

Read Cycle (Continue Burst)

Next

X

L

H

X

X

L

L

L-H

Data Out (Q)

NOP/Dummy Read (Begin Burst)

External

L

L

L

H

X

H

L

L-H

Tri-State

Dummy Read (Continue Burst)

Next

X

L

H

X

X

H

L

L-H

Tri-State

Write Cycle (Begin Burst)

External

L

L

L

L

L

X

L

L-H

Data In (D)

Write Cycle (Continue Burst)

Next

X

L

H

X

L

X

L

L-H

Data In (D)

NOP/Write Abort (Begin Burst)

None

L

L

L

L

H

X

L

L-H

Tri-State

Write Abort (Continue Burst)

Next

X

L

H

X

H

X

L

L-H

Tri-State

Ignore Clock Edge (Stall)

Current

X

L

X

X

X

X

H

L-H

–

Sleep Mode

None

X

H

X

X

X

X

X

X

Tri-State

Notes:

1.X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.

2.Write is defined by WE and BW[a:d]. See Write Cycle Description table for details.

3.When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.

4.The DQ and DQP pins are controlled by the current cycle and the OE signal.

5.CEN = H inserts wait states.

6.Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.

7.OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles.During a Read cycle DQs and DQP[a:d] = Tri-state when OE is inactive or when the device is deselected, and DQs = data when OE is active.

Document #: 38-05290 Rev. *I Page 8 of 28

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