NOP, Stall and Deselect Cycles21, 22 | Cypress CY7C1470V25 instruction

CY7C1470V25

CY7C1472V25

CY7C1474V25

Switching Waveforms (continued)

NOP, STALL and DESELECT Cycles[21, 22, 24]

1 2 3

CLK

CEN

ADV/LD

BWx

4	5	6	7	8	9	10

ADDRESS A1 A2

Data

In-Out (DQ)

WRITE	READ	STALL
D(A1)	Q(A2)

ZZ Mode Timing[25, 26]

CLK

A3	A4
D(A1)	Q(A2)	Q(A3)
READ	WRITE	STALL
Q(A3)	D(A4)

DON’T CARE

	A5
	D(A4)
NOP	READ
	Q(A5)

UNDEFINED

tCHZ

Q(A5)

DESELECT CONTINUE DESELECT

t ZZ

t ZZI

ISUPPLY

I DDZZ

ALL INPUTS (except ZZ)

Outputs (Q)

Notes:

High-Z

DON’T CARE

t ZZREC

t RZZI

DESELECT or READ Only

24.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A Write is not performed during this cycle.

25.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.

26.I/Os are in High-Z when exiting ZZ sleep mode.

Document #: 38-05290 Rev. *I

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Cypress CY7C1470V25, CY7C1474V25, CY7C1472V25 manual NOP, Stall and Deselect Cycles21, 22, ZZ Mode Timing25

CY7C1474V25, CY7C1470V25, CY7C1472V25 specifications

The Cypress CY7C1470V25, CY7C1474V25, and CY7C1472V25 are part of Cypress Semiconductor’s family of high-performance synchronous static random-access memory (SRAM) solutions. These memory devices are designed specifically for applications that require fast access times and high bandwidth, making them ideal for a variety of consumer and industrial applications.

One of the standout features of these SRAMs is their performance. They provide high-speed access times, with data transfer rates that can reach up to 1 GHz. This performance is particularly beneficial for high-speed applications including networking equipment, telecommunications, and video processing systems. The CY7C1470V25, for example, offers a 256K x 16 configuration with an access time as low as 3.5 ns. Similarly, the CY7C1474V25 and CY7C1472V25 variants provide respective memory sizes of 1M x 16 and 512K x 16, catering to diverse memory application needs.

These SRAMs utilize a synchronous interface, which provides greater control over data transfers and synchronization with external clock signals. This synchronous operation allows for more efficient data handling in high-speed environments, reducing latency and improving system performance overall.

In terms of power consumption, the Cypress CY7C147x series is designed to operate efficiently. With a low operating voltage of 2.5V, these devices minimize energy usage while still delivering high-speed performance. The low standby power makes them suitable for battery-operated devices, as well as for systems where energy efficiency is a priority.

Furthermore, these SRAMs come with built-in features such as burst mode, which allows for sequential data access, enhancing read and write operations. This is especially useful in applications requiring rapid data retrieval.

The packaging options for the CY7C1470V25, CY7C1474V25, and CY7C1472V25 include both fine-pitch ball grid array (FBGA) and other configurations, facilitating easy integration into various circuit board layouts.

In conclusion, the Cypress CY7C1470V25, CY7C1474V25, and CY7C1472V25 SRAMs are powerful memory solutions that combine high-speed performance, low power consumption, and a synchronous interface. Their robust design makes them suitable for a wide array of applications ranging from communications to consumer electronics, ensuring they meet the demands of modern technology.

Contents

Logic Block Diagram-CY7C1470V25 2M x FeaturesFunctional Description Cypress Semiconductor Corporation Logic Block Diagram-CY7C1474V25 1M x Logic Block Diagram-CY7C1472V25 4M xSelection Guide 250 MHz 200 MHz 167 MHz Unit 4M × Pin Configurations Pin Tqfp Pinout CY7C1472V25 4M x Pin Definitions Pin Name Type Pin DescriptionByte Write Select Inputs, active L OW . Qualified with Power supply inputs to the core of the device Power supply for the I/O circuitryClock input to the Jtag circuitry Burst Read Accesses Single Read AccessesSingle Write Accesses Burst Write Accesses Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Function CY7C1470V25 BW d BW c BW b BW a Partial Write Cycle Description1, 2, 3Function CY7C1472V25 Function CY7C1474V25 Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller Block Diagram TAP Controller State Diagram TAP Instruction Set Instruction Register TAP Timing TAP AC Switching Characteristics Over the Operating Range9Parameter Description Min Max Unit Clock Output Times 5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions8V TAP AC Test Conditions Identification Register Definitions Identification Codes Scan Register SizesRegister Name Bit Size Instruction Code Description Boundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID A11 Boundary Scan Exit Order 1M xJ10 W10 Maximum Ratings Electrical Characteristics Over the Operating Range12Operating Range Ambient Range Capacitance14 Thermal Resistance14AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 15 250 200 167 Parameter Description Unit Min MaxSet-up Times Read/Write/Timing21, 22 Switching WaveformsAddress A1 A2 DON’T Care NOP, Stall and Deselect Cycles21, 22 ZZ Mode Timing25 Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams Ball Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. Description of Change VKN 472335 See ECN

Cypress CY7C1470V25, CY7C1474V25 manual NOP, Stall and Deselect Cycles21, 22, ZZ Mode Timing25

Models: CY7C1474V25 CY7C1470V25 CY7C1472V25

Switching Waveforms (continued)

NOP, STALL and DESELECT Cycles[21, 22, 24]

ZZ Mode Timing[25, 26]

CY7C1474V25, CY7C1470V25, CY7C1472V25 specifications