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Cypress CY7C1471V25, CY7C1473V25, CY7C1475V25 Boundary Scan Exit Order (2M x 36), Boundary Scan Exit Order (4M x 18)

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CY7C1471V25

CY7C1473V25

CY7C1475V25

Document #: 38-05287 Rev. *I Page 19 of 32

Boundary Scan Exit Order (2M x 36)

Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID

1C1 21R3 41J11 61B7

2 D1 22 P2 42 K10 62 B6

3 E1 23 R4 43 J10 63 A6

4D2 24P6 44H11 64B5

5E2 25R6 45G11 65A5

6F1 26 R8 46F11 66A4

7G1 27 P3 47E11 67B4

8 F2 28 P4 48 D10 68 B3

9G2 29 P8 49D11 69A3

10 J1 30 P9 50 C11 70 A2

11 K1 31 P10 51 G10 71 B2

12 L1 32 R9 52 F10

13 J2 33 R10 53 E10

14 M1 34 R11 54 A9

15 N1 35 N11 55 B9

16 K2 36 M11 56 A10

17 L2 37 L11 57 B10

18 M2 38 M10 58 A8

19 R1 39 L10 59 B8

20 R2 40 K11 60 A7

Boundary Scan Exit Order (4M x 18)

Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID

1 D2 14 R4 27 L10 40 B10

2E2 15 P6 28K10 41A8

3F2 16 R6 29J10 42B8

4G2 17 R8 30H11 43A7

5J1 18 P3 31G11 44B7

6K1 19 P4 32F11 45B6

7L1 20 P8 33E11 46A6

8M1 21 P9 34D11 47B5

9 N1 22 P10 35 C11 48 A4

10 R1 23 R9 36 A11 49 B3

11 R2 24 R10 37 A9 50 A3

12 R3 25 R11 38 B9 51 A2

13 P2 26 M10 39 A10 52 B2

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Contents

Main 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture CY7C1471V25 CY7C1473V25 CY7C1475V25 Features Functional Description Selection Guide CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev. *I Page 2 of 32 Logic Block Diagram CY7C1471V25 (2M x 36) C B CY7C1473V25 Document #: 38-05287 Rev. *I Page 3 of 32 Logic Block Diagram CY7C1475V25 (1M x 72) DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh CY7C1471V25 CY7C1473V25 CY7C1475V25 Pin Configurations 100-Pin TQFP Pinout CY7C1471V25 CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev. *I Page 5 of 32 100-Pin TQFP Pinout CY7C1473V25 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1471V25 (2M x 36) 2345671 A B C D E F G H J K L M N P R 891011 CY7C1473V25 (4M x 18) 2345671 A B C D E F G H J K L M N P R CY7C1471V25 CY7C1473V25 CY7C1475V25 CY7C1475V25 (1M 72) Document #: 38-05287 Rev. *I Page 7 of 32 A B C D E F G H J K L M N P R T U V W 12 34 5 6 789 1110 Pin Definitions Functional Overview Pin Definitions Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Page IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Controller State Diagram TAP Controller Block Diagram CY7C1471V25 CY7C1473V25 CY7C1475V25 TAP Ti ming TAP AC Switching Characteristics 1.8V TAP AC Test Conditions 2.5V TAP AC Test Conditions 50 TDO 50 Scan Register Sizes Identification Codes Boundary Scan Exit Order (2M x 36) Boundary Scan Exit Order (4M x 18) Boundary Scan Exit Order (1M x 72) Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Figure1 shows re ad-write timing waveform.[19, 20, 21] Figure 1. Read/Write Timing 123456789 CLK 10 DONT CARE UNDEFINED OE BW CY7C1471V25 CY7C1473V25 CY7C1475V25 Figure3 shows ZZ Mode timing waveform.[23, 24] Figure 3. ZZ Mode Timing Switching Waveforms Ordering Information Document #: 38-05287 Rev. *I Page 28 of 32 Package Diagrams Figure 4. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 A Figure 5. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165 Package Diagrams 51-85165-*A Page Document History Page