CY7C1471V25
CY7C1473V25
CY7C1475V25
Document #: 38-05287 Rev. *I Page 31 of 32
Document History Page
Document Title: CY7C1471V25/CY7C1473V25/CY7C1475V25, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
with NoBL™ Architecture
Document Number: 38-05287
REV. ECN NO. Issue
Date
Orig. of
Change Description of Change
** 114674 08/06/02 PKS New Data Sheet
*A 121522 01/27/03 CJM Updated features for package offering
Updated ordering information
Changed Advanced Information to Preliminary
*B 223721 See ECN NJY Changed timing diagrams
Changed logic block diagrams
Modified Functional Description
Modified “Functional Overview” section
Added boundary scan order for all packages
Included thermal numbers and capacitance values for all packages
Removed 150MHz speed grade offering
Included ISB and IDD values
Changed package outline for 165FBGA package and 209-Ball BGA package
Removed 119-BGA package offering
*C 235012 See ECN RYQ Minor Change: The data sheets do not match on the spec system and
external web
*D 243572 See ECN NJY Changed ball H2 from VDD to NC in the 165-Ball FBGA package in page 6
Changed ball R11 in 209-Ball BGA package from DQPa to DQPe in page 7
Modified Capacitance values on page 21
*E 299511 See ECN SYT Removed 117-MHz Speed Bin
Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for 100
TQFP Package on Page # 22
Added Pb-free information for 100-Pin TQFP, 165 FBGA and 209 BGA
Packages
Added comment of ‘Pb-free BG packages availability’ below the Ordering
Information
*F 323039 See ECN PCI Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added Address Expansion pins in the Pin Definitions Table
Modified VOL, VOH Test Conditions
Changed package name from 209-Ball PBGA to 209-Ball FBGA on page# 7
Added Industrial temperature range
Added Pb-free information in the ordering information table
Removed comment of ‘Pb-free BG packages availability’ below the Ordering
Information
Updated Ordering Information Table
*G 416221 See ECN NXR Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed the description of IX from Input Load Current to Input Leakage
Current on page# 20
Changed the IX current values of MODE on page # 20 from –5 µA and 30 µA
to –30 µA and 5 µA
Changed the IX current values of ZZ on page # 20 from –30 µA and 5 µA
to –5 µA and 30 µA
Changed VIH < VDD to VIH < VDD on page # 20
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information table
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