Cypress CY7C1471V25, CY7C1473V25, CY7C1475V25 Switching Characteristics

CY7C1471V25
CY7C1473V25
CY7C1475V25
Document #: 38-05287 Rev. *I Page 23 of 32
Switching Characteristics
Over the Operating Range. Timing reference level is 1.25V when VDDQ = 2.5V and is 0.9V when VDDQ = 1.8V. Test conditions
shown in (a) of “AC Test Loads and Waveforms” on page22 unless otherwise noted.
Parameter Description 133 MHz 100 MHz Unit
Min Max Min Max
tPOWER 11ms
Clock
tCYC Clock Cycle Time 7.5 10 ns
tCH Clock HIGH 2.5 3.0 ns
tCL Clock LOW 2.5 3.0 ns
Output Times
tCDV Data Output Valid After CLK Rise 6.5 8.5 ns
tDOH Data Output Hold After CLK Rise 2.5 2.5 ns
tCLZ Clock to Low-Z [16, 17, 18] 3.0 3.0 ns
tCHZ Clock to High-Z [16, 17, 18] 3.8 4.5 ns
tOEV OE LOW to Output Valid 3.0 3.8 ns
tOELZ OE LOW to Output Low-Z [16, 17, 18] 00ns
tOEHZ OE HIGH to Output High-Z [16, 17, 18] 3.0 4.0 ns
Setup Times
tAS Address Setup Before CLK Rise 1.5 1.5 ns
tALS ADV/LD Setup Before CLK Rise 1.5 1.5 ns
tWES WE, BWX Setup Before CLK Rise 1.5 1.5 ns
tCENS CEN Setup Before CLK Rise 1.5 1.5 ns
tDS Data Input Setup Before CLK Rise 1.5 1.5 ns
tCES Chip Enable Setup Before CLK Rise 1.5 1.5 ns
Hold Times
tAH Address Hold After CLK Rise 0.5 0.5 ns
tALH ADV/LD Hold After CLK Rise 0.5 0.5 ns
tWEH WE, BWX Hold After CLK Rise 0.5 0.5 ns
tCENH CEN Hold After CLK Rise 0.5 0.5 ns
tDH Data Input Hold After CLK Rise 0.5 0.5 ns
tCEH Chip Enable Hold After CLK Rise 0.5 0.5 ns
Notes
15.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation
can be initiated.
16.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page22. Transition is measured ±200mV
from steady-state voltage.
17.At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z before Low-Z under the same system conditions.
18.This parameter is sampled and not 100% tested.
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