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Cypress CY7C1471V25, CY7C1473V25, CY7C1475V25 CY7C1471V25 CY7C1473V25 CY7C1475V25

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CY7C1471V25CY7C1473V25CY7C1475V25

Document #: 38-05287 Rev. *I Page 7 of 32

Pin Configurations (continued)

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

12 34 5 6 789 1110

DQg

DQg

DQg

DQg

DQg

DQg

DQg

DQg

DQc

DQc

DQc

DQc

NC

DQPg

DQh

DQh

DQh

DQh

DQd

DQd

DQd

DQd

DQPd

DQPc

DQc

DQc

DQc

DQc

NC

DQh

DQh

DQh

DQh

DQPh

DQd

DQd

DQd

DQd

DQb

DQb

DQb

DQb

DQb

DQb

DQb

DQb

DQf

DQf

DQf

DQf

NC

DQPf

DQa

DQa

DQa

DQa

DQe

DQe

DQe

DQe

DQPa

DQPb

DQf

DQf

DQf

DQf

NC

DQa

DQa

DQa

DQa

DQPe

DQe

DQe

DQe

DQe

AA A A

NC NC

NC/144M AA NC/288M

AAA

AAAA1

A0

AAA

AA

A

NC/576M

NC

NC

NC NC

NC

BWSbBWSf

BWSeBWSa

BWScBWSg

BWSd

BWSh

TMS TDI TDO TCK

NC

NC MODE NC

CEN VSS

NC

CLK NC VSS

VDD VDD VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VSS VSS

VSS

VSS

VSS

VSS VSS

VSS

NC/1G

VDD

NC

OE

CE3

CE1

CE2ADV/LD

WE

VSS

VSS

VSS

VSS VSS VSS VSS

ZZ

VSS VSS VSS VSS

NC

VDDQ

VSS

VSS NC VSS VSS

VSS VSS VSS VSS

NC

VSS

VDDQ VDDQ VDDQ VDDQ

VDDQ NC VDDQ VDDQ

VDDQ VDDQ NC VDDQ VDDQ

VDDQ VDDQ NC VDDQ VDDQ

VDDQ

VDDQ

VDDQ VDDQ

VDDQ VDDQ VDDQ VDDQ

CY7C1475V25 (1M × 72)

209-Ball FBGA (14 x 22 x 1.76 mm) Pinout

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Contents

Main 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture CY7C1471V25 CY7C1473V25 CY7C1475V25 Features Functional Description Selection Guide CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev. *I Page 2 of 32 Logic Block Diagram CY7C1471V25 (2M x 36) C B CY7C1473V25 Document #: 38-05287 Rev. *I Page 3 of 32 Logic Block Diagram CY7C1475V25 (1M x 72) DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh CY7C1471V25 CY7C1473V25 CY7C1475V25 Pin Configurations 100-Pin TQFP Pinout CY7C1471V25 CY7C1471V25 CY7C1473V25 CY7C1475V25 Document #: 38-05287 Rev. *I Page 5 of 32 100-Pin TQFP Pinout CY7C1473V25 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1471V25 (2M x 36) 2345671 A B C D E F G H J K L M N P R 891011 CY7C1473V25 (4M x 18) 2345671 A B C D E F G H J K L M N P R CY7C1471V25 CY7C1473V25 CY7C1475V25 CY7C1475V25 (1M 72) Document #: 38-05287 Rev. *I Page 7 of 32 A B C D E F G H J K L M N P R T U V W 12 34 5 6 789 1110 Pin Definitions Functional Overview Pin Definitions Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Page IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Controller State Diagram TAP Controller Block Diagram CY7C1471V25 CY7C1473V25 CY7C1475V25 TAP Ti ming TAP AC Switching Characteristics 1.8V TAP AC Test Conditions 2.5V TAP AC Test Conditions 50 TDO 50 Scan Register Sizes Identification Codes Boundary Scan Exit Order (2M x 36) Boundary Scan Exit Order (4M x 18) Boundary Scan Exit Order (1M x 72) Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Figure1 shows re ad-write timing waveform.[19, 20, 21] Figure 1. Read/Write Timing 123456789 CLK 10 DONT CARE UNDEFINED OE BW CY7C1471V25 CY7C1473V25 CY7C1475V25 Figure3 shows ZZ Mode timing waveform.[23, 24] Figure 3. ZZ Mode Timing Switching Waveforms Ordering Information Document #: 38-05287 Rev. *I Page 28 of 32 Package Diagrams Figure 4. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 A Figure 5. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165 Package Diagrams 51-85165-*A Page Document History Page