Emerson MVME55006E manual L3 Cache, System Controller, ProcessorFunctional Description

ProcessorFunctional Description

Table 2-1 MVME5500 Features Summary (continued)

Feature	Description
PCI Mezzanine Cards	– Two PMC sites (one shared with the expansion memory and has
	IPMC capability)
PCI Expansion	– One expansion connector for interface to PMCspan
Miscellaneous	– Reset/Abort switch
	– Front-panel status indicators, Run and Board Fail
Form Factor	– Standard VME

2.4Processor

The MVME5500 supports the MPC7457 processor in the 483-pin CBGA package. The processor consists of a processor core, an internal 256KB L2 and an internal L3 tag and controller, which supports a backside L3 cache.

2.5L3 Cache

The MVME5500 uses two 8Mb DDR synchronous SRAM devices for the processor’s L3 cache data SRAM. This gives the processor a total of 2MB of L3 cache. These SRAM devices require a 2.5V core voltage. The MVME5500 provides 1.5V as the SRAM I/O voltage. The L3 bus operates at 200 MHz.

2.6System Controller

The GT-64260B system controller for PowerPC architecture processors is a single chip solution that provides the following features:

zA 64-bit interface to the CPU bus

zA 64-bit SDRAM interface

zA 32-bit generic device interface for Flash, etc.

zTwo 64-bit, 66 MHz PCI bus interfaces

zThree 10/100Mb Ethernet MAC ports (two ports not used)

zA DMA engine for moving data between the buses

zAn interrupt controller

zAn I2C device controller

zPowerPC bus arbiter

zCounter/timers

zWatchdog timer

MVME55006E Single-Board Computer Installation and Use (6806800A37D) 39