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MVME6100 manual
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57 pages, 219 Kb
MVME6100
Single-Board Computer
Programmer’s Reference
Guide
V6100A/PG1
July 2004 Edition
Contents
Main
Page
Safety Summary
Warning
Flammability
EMI Caution
Lithium Battery Caution
CE Notice (European Community)
Notice
Limited and Restricted Rights Legend
Contents
Page
Page
List of Tables
About This Guide
Overview of Contents
Comments and Suggestions
Conventions Used in This Manual
1Board Description and Memory Maps
Introduction
Overview
The following table lists the features of the MVME6100.
Table 1-1. MVME6100 Features Summary
Table 1-1. MVME6100 Features Summary (continued)
1-4 Computer Group Literature Center Web Site
Board Description and Memory Maps
Figure 1-1. MVME6100 Board Layout Diagram
Memory Maps
Default Processor Memory Map
Table 1-2. Default Processor Address Map
Note Set by configuration resistors.
Table 1-2. Default Processor Address Map (continued)
MOTLoads Processor Memory Map
MOTLoads processor memory map is given in the following table.
Table 1-3. MOTLoads Processor Address Map
Default PCI Memory Map
Table 1-4. Default PCI Address Map
Page
range assigned to Device Bank 1. The memory map is defined in the following table:
Table 1-6. Device Bank 1 I/O Memory Map
System Status Register 1
Table 1-7. System Status Register 1
Page
System Status Register 2
Table 1-8. System Status Register 2
Page
System Status Register 3
Table 1-9. System Status Register 3
Presence Detect Register
Table 1-10. Presence Detect Register
Configuration Header/Switch Register (S1)
Table 1-11. Configuration Header/Switch Register
ON ON
Time Base Enable Register
Quad Universal Asynchronous Receiver/Transmitter (UART)
Table 1-12. TBEN Register
Real-Time Clock and NVRAM
Table 1-13. M48T37V Access
2Programming Details
Introduction
MV64360 Multi-Purpose Port Configuration
2
MVME6100 board.
Table 2-1. MV64360 MPP Pin Function Assignments
MV64360 Reset Configuration
Table 2-1. MV64360 MPP Pin Function Assignments (continued)
2
Table 2-2. MV64360 Power-Up Configuration Settings
Page
Page
Page
Flash Memory
Real-Time Clock and NVRAM
Two-Wire Serial Interface
Table 2-3. M48T37V Access
2
DDR DRAM Serial Presence Detect
Table 2-4. I2C Bus Device Addressing
MV64360 Initialization
VPD and User Configuration EEPROMs
Temperature Sensor
MV64360 Device Controller Bank Assignments
MPC Bus and PCI Bus Arbitration
PCI Bus 0 and PCI Bus 1 Local Buses
PCI Mode/Frequency Selection
Table 2-5. Device Bank Assignments
PCI Configuration Space
Table 2-6. IDSEL Mapping for PCI Devices
2PCI Arbitration Assignments for MV64360 ASIC
PCI Bus 1 Local Bus PMC Expansion Slots
Table 2-7. PCI Arbitration Assignments for MV64360 ASIC
Figure 2-1. PCI Bus 1 Local Bus PMC Expansion Slots
PCI Bus 0 Local Bus Devices
2
MV64360 Interrupt Controller
Table 2-8. MV64360 Interrupt Assignments
Table 2-8. MV64360 Interrupt Assignments (continued)
2
MV64360 Endian Issues
A
ARelated Documentation
Motorola Computer Group Documents
Table A-1. Motorola Computer Group Documents
Manufacturers Documents
Table A-2. Manufacturers Documents
Page
Table A-2. Manufacturers Documents (continued)
Related Specifications
Table A-3. Related Specifications
Index