Device Bank 1 I/O Memory Map, Address Definition

Board Description and Memory Maps

range assigned to Device Bank 1. The memory map is defined in the following table:

Table 1-6. Device Bank 1 I/O Memory Map

Address			Definition

F110 0000			System Status Register 1

F110 0001			System Status Register 2

F110 0002			System Status Register 3

F110	0003		Reserved

F110	0004		Presence Detect Register

F110	0005		Software Readable Header/Switch

F110	0006		Timebase Enable Register

F110	0008	-F110 FFFF	Reserved for onboard registers

F111	0000	-F111 7FFF	M48T37V NVRAM/RTC

F112	0000	-F112 0FFF	COM 1 UART

F112	1000	-F112 0FFF	COM 2 UART

F112	2000	-F112 0FFF	Reserved (undefined)

F112	3000	-F11F FFFF	Reserved (undefined)

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Emerson MVME6100 manual Device Bank 1 I/O Memory Map, Address Definition, M48T37V NVRAM/RTC, COM 1 Uart, COM 2 Uart

Contents

MVME6100 Single-Board Computer Programmer’s Reference GuidePage Ground the Instrument Safety Summary EMI Caution Lithium Battery CautionFlammability CE Notice European Community Limited and Restricted Rights Legend Contents Appendix a List of Figures List of Tables Model Number Description About This Guide Comments and Suggestions Overview of Contents Bold Conventions Used in This Manual Overview Introduction Nvram MVME6100 Features SummaryFeature Description PCI/PMC MVME6100 Board Layout Diagram Processor Address Start End Size Definition Default Processor Memory MapDefault Processor Address Map Memory Maps F100 Ffff 29FF Ffff41FF Ffff F0FF Ffff MOTLoad’s Processor Address Map MOTLoad’s Processor Memory Map PCI Address Start End Size Definition Default PCI Memory MapDefault PCI Address Map MOTLoad’s PCI Memory Maps MOTLoad’s PCI Memory MapsVME Memory Map System I/O Memory Map COM 1 Uart Device Bank 1 I/O Memory MapAddress Definition M48T37V NVRAM/RTC Banksel System Status RegisterSystem Status Register Refclk Srominit AbortlFlashbsyl Fusestat System Status Register 2- 0xF1100001 BdfailEepromwp Flashawp Fbawphdr FbootbwpFbootbwphdr Tstatmask System Status Register 3- 0xF1100002 BoardresetReset Board Rsvd EREADY1 Presence Detect Register10. Presence Detect Register Ipmcprsnt PMC0PL Configuration Header/Switch Register S111. Configuration Header/Switch Register Pcieprsntl 3 4 5 6 7 TBEN0 Time Base Enable RegisterQuad Universal Asynchronous Receiver/Transmitter Uart 12. Tben Register Address Offset Function 0xF1110000 13. M48T37V AccessReal-Time Clock and Nvram Programming Details MV64360 Multi-Purpose Port Configuration MPP Pin Input Number Output Function MV64360 MPP Pin Function Assignments MV64360 Reset Configuration Srom MV64360 Power-Up Configuration Settings MV64360 Power-Up Configuration Settings PCI1 DLL Dram BADR0 PCI0 DLLMII/GMII GMII/PCS Dram PLL N TBD Real-Time Clock and Nvram Flash Memory M48T37V Access Two-Wire Serial Interface Device Function Size A2A1A0 Address DDR Dram Serial Presence DetectI2C Bus Device Addressing Device Address MV64360 Device Controller Bank Assignments VPD and User Configuration EEPROMsTemperature Sensor MV64360 Initialization Device Bank Assignments MPC Bus and PCI Bus ArbitrationPCI Bus 0 and PCI Bus 1 Local Buses PCI Mode/Frequency Selection Idsel AD20 PCI Configuration SpaceIdsel Mapping for PCI Devices MPP Pin Assignment PCI Masters PCI Arbitration Assignments for MV64360 AsicPCI Bus 1 Local Bus PMC Expansion Slots PCI Arbitration Assignments for MV64360 PCI Bus 1 Local Bus PMC Expansion Slots PCI Bus 0 Local Bus Devices Group MV64360 Edge/Level Polarity Interrupt Source MV64360 Interrupt ControllerMV64360 Interrupt Assignments PCI-PMC 0 INTD#, PMC INTB# PCI-PMC 0 INTC#, PMC INTA# DS1621 Digital Thermometer and Thermostat provides MV64360 Endian Issues Document Title Motorola Publication Number Motorola Computer Group DocumentsTable A-1. Motorola Computer Group Documents MPC7457EC/D Manufacturers’ DocumentsTable A-2. Manufacturers’ Documents Document Title and Source Publication Number Manufacturers’ Documents Table A-2. Manufacturers’ Documents Table A-3. Related Specifications Related Specifications Index

Emerson MVME6100 Device Bank 1 I/O Memory Map, Address Definition, M48T37V NVRAM/RTC, COM 1 Uart

Models: MVME6100

Table 1-6. Device Bank 1 I/O Memory Map

Address

Definition

M48T37V NVRAM/RTC

COM 1 UART

COM 2 UART