Flash Memory, Real-Time Clock and Nvram | Emerson MVME6100 instruction

Programming Details

2Table 2-2. MV64360 Power-Up Configuration Settings (continued)

Device		Default
AD Bus	Select	Power-Up
Signal	Option	Setting	Description	State of Bit vs. Function

TxD0[7]	Resistor	0	JTAG Pad	0	Normal Operation
			Calib Bypass
			Calib Bypass	1	Bypass pad calibration
				1	Bypass pad calibration

TxD1[1]	Resistor	0	Core PLL	0	Normal Operation
			Bypass
			Bypass	1	Bypass the core’s PLL
				1	Bypass the core’s PLL

TxD1[4:2]	Resistors	000	Core PLL	000	Tuning of the core PLL
			Control		clock tree.

Flash Memory

The MVME6100 contains two banks of flash memory accessed via the Device Controller bus contained within MV64360. Each bank contains from 8MB to 64MB of 32-bit wide Boot Block flash memory provided by two 16-bit wide Intel StrataFlash devices.

The Boot Bank is jumper selectable to select either flash bank as the boot bank. The jumper effectively swaps the chip selects to the two flash banks so that either bank can be used as the boot bank. The state of the jumper is readable in the BANK_SELECT bit of System Status Register 1 to properly set up the MV64360 Device Controller Bus memory maps.

The boot device bank is the same as any of the other device banks except that its default address map matches the PowerPC CPU boot address (0xfff0.0100) and that its default width is sampled at reset.

Real-Time Clock and NVRAM

The Real-Time Clock/NVRAM/Watchdog Timer is implemented using a SGS-Thompson M48T37V Timekeeper SRAM, and M4T28-BR12SH1 SnapHat battery. Refer to the M48T37V data sheets for additional programming information. Refer to Appendix A, Related Documentation.

2-8	Computer Group Literature Center Web Site

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Emerson MVME6100 manual Flash Memory, Real-Time Clock and Nvram

Contents

MVME6100 Single-Board Computer Programmer’s Reference GuidePage Ground the Instrument Safety Summary EMI Caution Lithium Battery CautionFlammability CE Notice European Community Limited and Restricted Rights Legend Contents Appendix a List of Figures List of Tables Model Number Description About This Guide Comments and Suggestions Overview of Contents Bold Conventions Used in This Manual Overview Introduction Nvram MVME6100 Features SummaryFeature Description PCI/PMC MVME6100 Board Layout Diagram Default Processor Address Map Default Processor Memory MapMemory Maps Processor Address Start End Size Definition 41FF Ffff 29FF FfffF0FF Ffff F100 Ffff MOTLoad’s Processor Address Map MOTLoad’s Processor Memory Map PCI Address Start End Size Definition Default PCI Memory MapDefault PCI Address Map VME Memory Map MOTLoad’s PCI Memory MapsSystem I/O Memory Map MOTLoad’s PCI Memory Maps Address Definition Device Bank 1 I/O Memory MapM48T37V NVRAM/RTC COM 1 Uart System Status Register System Status RegisterRefclk Banksel Flashbsyl AbortlFusestat Srominit Eepromwp BdfailFlashawp System Status Register 2- 0xF1100001 Fbootbwphdr FbootbwpTstatmask Fbawphdr System Status Register 3- 0xF1100002 BoardresetReset Board Rsvd 10. Presence Detect Register Presence Detect RegisterIpmcprsnt EREADY1 11. Configuration Header/Switch Register Configuration Header/Switch Register S1Pcieprsntl PMC0PL 3 4 5 6 7 Quad Universal Asynchronous Receiver/Transmitter Uart Time Base Enable Register12. Tben Register TBEN0 Address Offset Function 0xF1110000 13. M48T37V AccessReal-Time Clock and Nvram Programming Details MV64360 Multi-Purpose Port Configuration MPP Pin Input Number Output Function MV64360 MPP Pin Function Assignments MV64360 Reset Configuration Srom MV64360 Power-Up Configuration Settings MV64360 Power-Up Configuration Settings PCI1 DLL Dram MII/GMII GMII/PCS PCI0 DLLDram PLL N TBD BADR0 Real-Time Clock and Nvram Flash Memory M48T37V Access Two-Wire Serial Interface I2C Bus Device Addressing DDR Dram Serial Presence DetectDevice Address Device Function Size A2A1A0 Address Temperature Sensor VPD and User Configuration EEPROMsMV64360 Initialization MV64360 Device Controller Bank Assignments PCI Bus 0 and PCI Bus 1 Local Buses MPC Bus and PCI Bus ArbitrationPCI Mode/Frequency Selection Device Bank Assignments Idsel AD20 PCI Configuration SpaceIdsel Mapping for PCI Devices PCI Bus 1 Local Bus PMC Expansion Slots PCI Arbitration Assignments for MV64360 AsicPCI Arbitration Assignments for MV64360 MPP Pin Assignment PCI Masters PCI Bus 1 Local Bus PMC Expansion Slots PCI Bus 0 Local Bus Devices Group MV64360 Edge/Level Polarity Interrupt Source MV64360 Interrupt ControllerMV64360 Interrupt Assignments PCI-PMC 0 INTD#, PMC INTB# PCI-PMC 0 INTC#, PMC INTA# DS1621 Digital Thermometer and Thermostat provides MV64360 Endian Issues Document Title Motorola Publication Number Motorola Computer Group DocumentsTable A-1. Motorola Computer Group Documents Table A-2. Manufacturers’ Documents Manufacturers’ DocumentsDocument Title and Source Publication Number MPC7457EC/D Manufacturers’ Documents Table A-2. Manufacturers’ Documents Table A-3. Related Specifications Related Specifications Index