Fairchild RC5050, RC5051 specifications Less heat sink required

AN50 APPLICATION NOTE

Two MOSFETs in parallel.

We recommend two MOSFETs used in parallel instead of one single MOSFET. The following significant advantages are realized using two MOSFETs in parallel:

•Significant reduction of Power dissipation. Maximum current of 14A with one MOSFET:

PMOSFET = (I2 RDS,ON)(Duty Cycle) =

(14)2(0.050*)(3.3+0.4)/(5+0.4-0.35) = 7.2 W

With two MOSFETs in parallel:

PMOSFET = (I2 RDS,ON)(Duty Cycle) =

(14/2)2(0.037*)(3.3+0.4)/(5+0.4-0.35) = 1.3W/FET

*Note: RDS,ON increases with temperature. Assume RDS,ON = 25mΩ at 25°C. RDS,ON can easily increase to 50mΩ at high temperature when using a single MOSFET. When using two MOSFETs in parallel, the

temperature effects should not cause the RDS,ON to rise above the listed maximum value of 37mΩ.

•Less heat sink required.

With power dissipation down to around one watt and with MOSFETs mounted flat on the motherboard, considerable less heat sink is required. The junction-to-case thermal resistance for the MOSFET package (TO-220) is typically at 2°C/W and the motherboard serves as an excellent heat sink.

• Higher current capability.

With thermal management under control, this on-board DC-DC converter is able to deliver load currents up to 14.5A with no performance or reliability concerns.

MOSFET Gate Bias

MOSFET can be biased by one of two methods: Charge Pump and 12V Gate Bias.

•Method 1. Charge pump (or Boostrap) method. Figure 5 employs a charge pump to provide gate bias. Capacitor CP is the charge pump deployed to boost the voltage of the RC5050 output driver. When the MOSFET switches off, the source of the MOSFET is at -0.6V. VCCQP is charged through the Schottky diode to 4.5V. Thus, the capacitor CP is charged to 5V. When the MOS- FET turns on, the source of the MOSFET voltage is equal to 5V. The capacitor voltage follows, and hence provides a voltage at VCCQP equal to 10V. The Schottky diode is required to provide the charge path when the MOSFET is off, and reverses bias when the VCCQP goes to 10V. The

charge pump capacitor, CP, needs to be a high Q, high fre- quency capacitor. A 1µF ceramic capacitor capacitor is

recommended here.

+5V
DS2
VCCQP	M1
HIDRV
CP	L1	RS
PWM/PFM		VO
Control
	DS1	CB
		65-AP50-01

Figure 5. Charge Pump Configuration

• Method 2. 12V Gate Bias.

Figure 6 illustrates how a 12V source can be used to bias the VCCQP. A 47 Ω resistor is used to limit the transient current into the VCCQP pin and a 1µF capacitor filter is used to filter the VCCQP supply. This method provides a higher gate bias voltage (VGS) to the MOSFET, and there-

fore reduces the RDS,ON of the MOSFET and reduces the power loss due to the MOSFET. Figure 7 shows how

RDS,ON reduces dramatically with VGS increases. A 6.2V Zener diode (D1) is placed to clamp the voltage at VCCQP to a maximum of 12V and ensure that the absolute maxi- mum voltage of the IC will not be exceeded

+5V
47Ω
+12V
D1
6.2V
VCCQP	M1
HIDRV
1µF	L1	RS
PWM/PFM		VO
Control
	DS1	CB
		65-AP50-02

Figure 6. 12V Gate Bias Configuration

	0.1
	0.09						R(DS)Fuji
	0.08
							R(DS)7060
)	0.07
(Ω	0.06						R(DS)706A
DS,ON	0.05						R(DS)-706AEL
	0.04
R
	0.03
	0.02
	0.01
	0
	1.5 2	2.5 3	3.5	4	5	6	7	8	9	10	11

Gate-Source Voltage, VGS (V)

Figure 7. RDS,ON vs. VGS for Selected MOSFETs

8